Abstract:
A circuit comprising: a first switch having: a first side connected to a first node; and a second side connected to a second capacitor's first side (2C1S); a second switch having: a first side connected to a second capacitor's second side (2C2S); and a second side connected to a first capacitor's first side (1C1S); a third switch having: a first side connected to a first capacitor's second side (1C2S); and a second side connected to a second node (2VN); a fourth switch having: a first side connected to 2C2S; and a second side connected to a third node (3VN); a fifth switch having: a first side connected to 2C1S; and a second side connected to 1C1S; a sixth switch having: a first side connected to 1C2S; and a second side connected to 3VN; a seventh switch having: a first side connected to 1C1S; and a second side connected to 2VN.
Abstract:
The present disclosure shows a hybrid regulator topology that can be more easily integrated and that can maintain high efficiency across a wide output and input voltage range, even with a small inductor. The hybrid regulator topology can include two types of regulators: a flying switched-inductor regulator and a step-down regulator that divides the input voltage into an M/N fraction of the input voltage. The disclosed embodiments of the hybrid regulator topology can reduce the capacitive loss of the flying switched-inductor regulator by limiting the voltage swing across the switches in the flying switched-inductor regulator. The disclosed embodiments of the hybrid regulator topology can reduce the inductor resistive loss of the flying switched-inductor regulator by operating the flying switched-inductor regulator at a high switching frequency and with a small amount of current flow through the inductor.
Abstract:
Circuits comprising: a capacitor; switches that, when State0, couple the capacitor in parallel with the load and, when State1, couple the capacitor in series with the load, wherein a first of the switches connects the capacitor to ground when in State0 and wherein a second of the switches connects the capacitor to an input voltage when in State1; a third switch, wherein a first side of the third switch is connected to the capacitor identically to one of the first switch and the second switch (OFWSW), wherein the third switch switches identically to the OFWSW, wherein the third switch is smaller than the OFWSW; a first resistor connected to the second side of the third switch; and a hardware processor that measures a current flowing through the first resistor and estimates the current provided to the load based on the current measured as flowing through the first resistor.
Abstract:
Circuits comprising: an inductor having a first side connected to V IN ; a first switch having a first side connected to a second side of the inductor and the second side is not connected to the second side of the inductor; a second switch having a first side connected to V IN ; a first capacitor having a first side connected to a second side of the second switch; a third switch having a first side connected to a second side of the first switch; a fourth switch having a first side connected to a second side of the third switch; a fifth switch having a first side connected to a second side of the first capacitor and to a second side of the fourth switch, and having a second side coupled to a voltage source; and a second capacitor having a first side connected to the first side of the fourth switch, and having a second side connected to the second side of the fifth switch.
Abstract:
The present disclosure shows ways to use multiple "integrated voltage regulator (IVR) units" to offer IVRs that can cover a wide range of specifications without having to design separate IVRs for different specifications. Instead of designing separate IVRs and paying for separate mask sets for IVRs targeting different specifications (e.g., different design and mask sets for 1A IVR, 5A IVR), the disclosed embodiments present ways to design and fabricate large numbers of the same unit IVRs (e.g., 1 A IVR) and decide how many of them to use post-fabrication to deliver different current specifications (e.g., use five 1A unit IVRs for 5A, use ten 1A unit IVRs for 10A). These disclosed embodiments reduce the mask cost of fabricating IVRs for different specifications and reduce design time by focusing on a single unit IVR.
Abstract:
The present disclosure shows a hybrid regulator topology that can be more easily integrated and that can maintain high efficiency across a wide output and input voltage range, even with a small inductor. The hybrid regulator topology can include two types of regulators: a flying switched-inductor regulator and a step-down regulator that divides the input voltage into an M/N fraction of the input voltage. The disclosed embodiments of the hybrid regulator topology can reduce the capacitive loss of the flying switched-inductor regulator by limiting the voltage swing across the switches in the flying switched-inductor regulator. The disclosed embodiments of the hybrid regulator topology can reduce the inductor resistive loss of the flying switched-inductor regulator by operating the flying switched-inductor regulator at a high switching frequency and with a small amount of current flow through the inductor.
Abstract:
This application relates to methods and apparatus for DC voltage conversion. A DC converter (100) is described, with a charge pump circuit comprising a plurality of charge pump stages (1401, 1402-2,1402-2) each charge pump stage comprising connections for respective first and second capacitors for that stage (C1A, C1B; C2A,C2B; C3A, C3B). The charge pump also has a switch network, wherein the switch network comprises, between each successive stage, four switching paths (S7AA, S7AB, S7Ba, S7BB; S6AA, S6AB, S6Ba, S6BB) for separately connecting a respective first electrode of each of the first and second capacitors of one stage to a first electrode either of the first and second capacitors of the preceding stage, so that the relevant capacitor of the one stage can be charged by the relevant capacitor of the preceding stage.
Abstract:
A voltage regulator comprising: a first regulator module comprising a first transistor switch, wherein the first module operates in a first phase and wherein the first switch is configured to receive a first signal at a first gate of the first switch from a first signal driver; a second regulator module comprising a second transistor switch, wherein the second module operates in a second phase that is different from the first phase, wherein the second switch is configured to receive a second gate drive signal at a second gate of the second switch from a second signal driver, and wherein the second signal is opposite in polarity from the first signal; and a switch that couples the first gate and the second gate during at least part of a time period during which the first switch transitions states and the second switch transitions states.
Abstract:
The present disclosure provides an asymmetric switching capacitor regulator that is capable of providing an output voltage, covering a wide voltage range, with a high efficiency. The disclosed switching capacitor regulator is configured to generate a wide range of an output voltage by differentiating a voltage across one or more switching capacitors from a voltage across the rest of the switching capacitors in the switching capacitor regulator.
Abstract:
An inductor; a first switch having a first side connected to a first voltage source (VS1); a second switch having a first side connected to a second side of the first switch (2SS1), and a second side connected to a first side of the inductor (1 SI); a third switch having a first side connected to the 1 SI; a fourth switch having a first side connected to a second side of the third switch (2SS3), and a second side connected to a second voltage source (VS2); a fifth switch having a first side connected to the 1 SI, and a second side connected to the VS1 and/or the VS2; a first capacitor having a first side connected to the 2SS1, and a second side connected to the 2SS3; and a second capacitor having a first side connected to a second side of the inductor, and a second side connected to the VS2.