Abstract:
In an example, a system-on-chip (SoC) includes a hardware power-on- reset (POR) sequencer circuit (142) coupled to a POR pin (135). The SoC further includes a platform management unit (PMU) (122), coupled to the hardware POR sequencer circuit, the PMU including one or more central processing units (CPUs) (304) and a read only memory (ROM) (312). The SoC further includes one or more processing units (116, 118, 120) configured to execute a boot process. The hardware POR sequencer circuit is configured to initialize the PMU. The one or more CPUs of the PMU are configured to execute code (334) stored in the ROM to perform a pre-boot initialization.
Abstract:
In one example of the present disclosure, a computing system is provided. The computing system is to initiate a power on self-test (POST) process, determine that a change has been made to system firmware configuration data, start a timer, and determine that the timer has expired. Thereafter, the computing system is to power-off and power-on the computing system, replace current system firmware configuration data with backup system firmware configuration data, and/or generate a notification indicating system firmware configuration data has been reverted.