Abstract:
A method and apparatus for turbo encoding with a contention-free interleaver is provided herein. During operation an input block of size K' is received. The original input block and the interleaved input block are encoded to obtain a codeword block, wherein the original input block is interleaved using an interleaver of size K' and a permutation π(i)= ( ƒ 1 x i + ƒ 2 x i 2 ) mod K', where O ≤ i ≤ K'-1 is the sequential index of the symbol positions after interleaving, π(i) is the symbol index before interleaving corresponding to position i, K' is the interleaver size in symbols, and/i and /2 are the factors defining the interleaver. The values of K', ƒ 1 , ƒ 2 are taken from at least one row of a table. The codeword block is transmitted through the channel.
Abstract translation:本文提供了一种用无竞争交织器进行turbo编码的方法和装置。 在操作期间,接收大小为K'的输入块。 编码原始输入块和交错输入块以获得码字块,其中原始输入块使用大小为K'的交织器和置换p(i)=(1×1×i + mod K',其中O = i = K'-1是交织后的符号位置的顺序索引,p(i)是符号索引 在对应于位置i的交织之前,K'是符号中的交织器大小,并且/ i和/ 2是定义交织器的因子。 K',< 1>,< 2> 2的值取自表的至少一行。 码字块通过信道传输。
Abstract:
L'invention concerne un procédé de codage d'un message numérique d'entrée, portant K symboles d'information, mettant en œuvre un turbo-codeur formant un turbocode et délivrant les symboles d'information et des symboles de redondance, un poinçonnage des symboles délivrés par le turbo- codeur étant effectué suivant au moins un motif ( M_P ) de poinçonnage de longueur N, L = K/N définissant le nombre de périodes de poinçonnage. Le turbocode permet le codage du message avec un rendement variable pouvant varier entre un premier rendement R 1 dit le plus faible et un second rendement R z , dit le plus élevé. Selon l'invention, le procédé (1) comprend : une optimisation conjointe (2) de l'entrelacement et du poinçonnage pour le rendement le plus élevé R z et ensuite - un ajout (3) d'une position non poinçonnée dans au moins un motif de poinçonnage pour au moins une période du au moins un motif pour une variation du rendement.
Abstract:
La présente invention concerne un procédé de codage d'un message numérique d'entrée, portant K symboles d'information, mettant en œuvre un turbo-encodeur formant un turbocode, le turbo-encodeur comportant un entrelaceur et des premier et deuxième encodeurs (C1, C2) à encodage selon au moins un code élémentaire, et délivrant les symboles d'information et des symboles de redondance. Selon l'invention, un poinçonnage des symboles délivrés par le turbo-encodeur étant effectué suivant au moins un motif de poinçonnage périodique de longueur N, définissant la période de poinçonnage N, ledit entrelaceur répartit les symboles d'information dudit message d'entrée dans Q couches du message d'entrée entrelacé en respectant une fonction d'entrelacement définie à partir dudit au moins un motif de poinçonnage, selon la relation π(i) = Pi + S(i mod Q) mod K = Pi + (T l + A l Q) mod K.
Abstract translation:本发明涉及使用形成turbo码的turbo编码器对具有K个信息符号的数字输入消息进行编码的方法,所述turbo编码器包括交织器和根据至少一个编码的第一和第二编码器(C1,C2) 基本代码,以及传递信息符号和冗余符号。 根据本发明,根据定义穿孔周期N的长度为N的至少一个周期性穿孔模式,执行由turbo编码器传送的符号的删截,所述交织器将所述输入消息的信息符号分配在Q个输入消息层 根据关系π(i)= Pi + S(i mod Q)mod K = Pi +(T1 + AlQ)modK,根据从所述至少一个打孔图案定义的交织功能进行交织。
Abstract:
본 출원에서는 이동 통신 시스템에서 송신측이 CTC(Convolutional Turbo Code) 인코더를 이용하여 데이터를 전송하는 방법이 개시된다. 구체적으로, 상기 CTC 인코더의 두 개의 입력단을 통해 입력받은 입력 데이터 비트들을 인코딩하여 제 1 인코딩 비트들을 출력하는 제 1 인코딩 단계; 상기 입력 데이터 비트의 크기에 대응하는 4개의 CTC 인터리버 파라미터(P0, P1, P2 및 P3)를 이용하여 상기 입력 데이터 비트들을 인터리빙하는 단계; 상기 인터리빙된 데이터 비트들을 인코딩하여 제 2 인코딩 비트들을 출력하는 제 2 인코딩 단계; 및 소정 코딩율에 따라 상기 입력 데이터 비트들, 상기 제 1 인코딩 비트들 및 상기 제 2 인코딩 비트들을 선택적으로 수신측에 전송하는 단계를 포함하되, 상기 입력 데이터 비트의 크기에 대응되는 CTC 인터리버 파라미터 중 P0는 상기 입력 데이터 비트들의 크기의 1/2인 N과 서로 소(relative prime number)이고, P2는 N-1의 값을 가지며, P1과 P2의 차는 1인 것을 특징으로 한다.
Abstract:
A data processing system, a turbo decoding system, an address generator and a method of reconfiguring a turbo decoding method is provided. The data processing system (101) comprises the turbo decoding system (100). The turbo decoding system (100) comprises electronic circuits. The electronic circuits comprises: a memory (108), the address generator (102), and a Soft Input Soft Output decoder (106). The address generator (102) is operative to produce a sequence of addresses according to an interleaving scheme. The address generator can support multiple interleaving schemes. The address generator (102) is operative to receive reconfiguration information. The address generator (102) is operative to reconfigure during operational use the interleaving scheme in dependency on the reconfiguration information.
Abstract:
An interleaver provision method for providing a continuous length, an interleaving method, and a turbo- encoder thereof are disclosed. The interleaving method selects a basic interleaver having a proper length from among the basic interleaver set, which is predetermined to have the length represented by a multiple of the ARP fluctuation vector period. The interleaving method performs the dummy insertion and the pruning process to have the length acting as the basic-interleaver length, so that it can provide the ARP interleaver having a continuous length.
Abstract:
The present invention relates to an apparatus and method for interleaving within a communication system. The apparatus and the associated method relate to a turbo interleaver for duo-binary turbo codes, which are also denoted as CTC codes, as defined in the IEEE 802.16e WiMAX specification. The apparatus for interleaving comprises an interleaver (100), and a memory device (200). The memory device (200) further includes M independent memory rows, wherein M is a multiple of k. The interleaver (100) further includes M address registers (120), a first switch (110), M select-swap circuit (130), a second switch (120), a couple merging circuit (150) and M-byte output registers (160).
Abstract:
An interleave address generating circuit of a multicore type turbo decode processing apparatus of the present invention includes intermediate value generating blocks whose arithmetic portions are modified so as to generate not only an interleave address corresponding to the forward direction but also an interleave address corresponding to the backward direction. By using initial parameters which are preliminarily decomposed into parameters for a memory bank and physical addresses, the intermediate value generating blocks having a restricted bit width in two parallel are disposed in two parallel and the two intermediate value generating blocks are connected to each other through signal lines for exchanging carry signals.
Abstract:
A method for interleaving continuous length sequence is disclosed. The interleaving method selects a basic interleaver (S601 ) having a proper length from among the basic interleaver set, which is predetermined to have the length represented by a multiple of the ARP fluctuation vector period. The interleaving method performs the dummy insertion (S602) and the pruning process to have the length acting as the basic-interleaver length, so that it can provide the ARP interleaver (S603) having a continuous length.