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2.发明申请FLOATING-POINT ADDER WITH OPERAND SHIFTING BASED ON A PREDICTED EXPONENT DIFFERENCE 审中-公开基于预测出现差异的具有操作移位的浮点指示
公开(公告)号：WO2013123472A3
公开(公告)日：2014-01-23
申请号：PCT/US2013026560
申请日：2013-02-17
Applicant: QUALCOMM INC
Inventor： DOCKSER KENNETH A , LALL PATHIK SUNIL
IPC: G06F7/485
CPC classification number: G06F7/485
Abstract: Provided are a floating-point adder and methods for implementing a floating-point adder with operand shifting based on a predicted exponent difference when performing an effective subtraction on normal or subnormal numbers. In an aspect, two least significant bits (LSBs) of a first floating-point operand's exponent are compared with two LSBs of a second floating-point operand's exponent to estimate a difference between the two exponents. A first shift of up to one of the first and the second operands is performed, based on the estimated difference. A prospective result is then produced by subtracting the first operand and the second operand. Contemporaneously, one of the first operand's exponent and the second operand's exponent is subtracted from the other of the first operand's exponent and the second operand's exponent to determine if the exponents actually differ by one or less. If the first operand's exponent and the second operand's exponent differ by one or less, the prospective result is provided as the raw difference of the operands.
Abstract translation: 提供了一种浮点加法器和用于在对正常或正常数进行有效减法时，基于预测指数差来实现具有操作数移位的浮点加法器的方法。 在一方面，将第一浮点运算数的指数的两个最低有效位（LSB）与第二浮点运算指数的两个LSB进行比较，以估计两个指数之间的差。 基于估计的差异，执行高达第一和第二操作数之一的第一移位。 然后通过减去第一操作数和第二操作数产生预期结果。 同时，第一个操作数的指数和第二个操作数的指数之一从第一个操作数的指数和第二个操作数的指数的另一个中减去，以确定指数实际上是否相差一个或更少。 如果第一个操作数的指数和第二个操作数的指数相差一个或几个，则预期结果作为操作数的原始差异提供。
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公开(公告)号：WO2023078364A1
公开(公告)日：2023-05-11
申请号：PCT/CN2022/129619
申请日：2022-11-03
Applicant: 深圳市中兴微电子技术有限公司
Abstract: 本发明实施例提供了一种矩阵乘法的运算方法及装置，所述运算方法包括：将两个2N比特的浮点型数据分别拆分为对应的符号位、精度位和指数位，以及将四个N比特的整型数据分别拆分为对应的符号位和精度位；通过指数位相加、符号位异或和精度位相乘对所述两个浮点型数据进行矩阵乘法运算，以及通过符号位异或和精度位相乘对所述四个整型数据两两进行矩阵乘法运算，并在所述浮点型数据和所述整型数据的矩阵乘法运算中复用乘法单元和加法单元。在本发明中，通过将不同数据类型的输入数据进行拆分，从而可以在矩阵乘法过程中复用加速器的乘法和加法运算资源，从而大大减少了加速器的芯片面积和降低了成本。
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公开(公告)号：WO2023070997A1
公开(公告)日：2023-05-04
申请号：PCT/CN2022/077275
申请日：2022-02-22
Applicant: 中国科学院计算技术研究所
Abstract: 本发明提出一种利用比特级稀疏性的深度学习卷积加速方法和处理器，包括：获取待卷积的多组数据对，求和每组数据对中激活值和原始权重的指数，得到每一组数据对的指数和，并从所有数据对中选择数值最大的指数和作为最大指数；按计算顺序排列原始权重的尾数，形成权重矩阵，并将权重矩阵中各行统一对齐到最大指数，得到对齐矩阵；剔除对齐矩阵中的松弛位，得到精简矩阵，精简矩阵每一列的基本位按计算顺序递补空位，形成中间矩阵，剔除中间矩阵的空行后，将矩阵中空位置0，得到交错权重矩阵，将交错权重矩阵中每一行中权重段与对应激活值的尾数发送至加法树进行求和处理，通过对处理结果执行移位相加，得到输出特征图作为多组数据对的卷积结果。
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5.发明申请
公开(公告)号：WO2017192243A3
公开(公告)日：2017-11-09
申请号：PCT/US2017/026910
申请日：2017-04-11
Applicant: ALTERA CORPORATION
Inventor： LANGHAMMER, Martin
Abstract: The present embodiments relate to circuitry that efficiently performs floating-point arithmetic operations and fixed-point arithmetic operations. Such circuitry may be implemented in specialized processing blocks. If desired, the specialized processing blocks may include configurable interconnect circuitry to support a variety of different use modes. For example, the specialized processing block may efficiently perform a fixed-point or floating-point addition operation or a portion thereof, a fixed-point or floating-point multiplication operation or a portion thereof, a fixed-point or floating-point multiply-add operation or a portion thereof, just to name a few. In some embodiments, two or more specialized processing blocks may be arranged in a cascade chain and perform together more complex operations such as a recursive mode dot product of two vectors of floating-point numbers or a Radix-2 Butterfly circuit, just to name a few.
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Patent Agency Ranking
公开(公告)号：WO99040508A1
公开(公告)日：1999-08-12
申请号：PCT/US1999/002455
申请日：1999-02-05
CPC classification number: G06F7/485
Abstract: A system for adding or subtracting numbers in signed floating point notation performs exponent and mantissa handling operations in parallel. The system includes a comparator (106), for determining a greater-magnitude and a lesser magnitude floating point number, operating in parallel with a selector (108) for performing a one's complement and single-bit shift on a mantissa portion of the lesser-magnitude floating point number. The system further includes a remaining shift circuit (110), for determining an additional amount by which the lesser-magnitude mantissa portion should be shifted; and a shifter (102). The system also includes an absolute add circuit (102), for determining whether an absolute addition or an absolute subtraction is to be performed, and a single-bit shift circuit (104), for indicating whether a shift of at least one bit is required.
Abstract translation: 用符号浮点符号加数或减数的系统并行执行指数和尾数处理操作。 该系统包括用于确定与选择器（108）并行操作的较大幅度和较小幅度的浮点数的比较器（106），用于在较小值的尾数部分上执行补码和单位移位， 大小浮点数。 该系统还包括剩余移位电路（110），用于确定较小量值尾数部分应移动的附加量; 和移位器（102）。 该系统还包括用于确定是否执行绝对加法或绝对减法的绝对加法电路（102），以及用于指示是否需要至少一个位的移位的单位移位电路（104） 。
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公开(公告)号：WO2022088157A1
公开(公告)日：2022-05-05
申请号：PCT/CN2020/125676
申请日：2020-10-31
Applicant: 华为技术有限公司
IPC: G06F7/485
Abstract: 一种浮点数计算电路（100）以及浮点数计算方法，浮点数计算电路（100）包括的拆分电路（102）拆分第一浮点数的尾数部分与第二浮点数的尾数部分。指数处理电路（104）得到拆分后的各尾数部分的第二移位数。计算电路（105）根据拆分后的各尾数部分以及拆分后的各尾数部分的第二移位数计算第一浮点数与所述第二浮点数的尾数部分的乘积。该浮点数计算电路（100）可以把位数较大的浮点数拆分为位数较小的浮点数，从而采用较小位数的乘法器来计算该位数较大的浮点数，该浮点数计算电路（100）时序开销短，硬件设计代价低，合理的利用了乘法器的计算性能。
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公开(公告)号：WO2020046546A1
公开(公告)日：2020-03-05
申请号：PCT/US2019/045418
申请日：2019-08-07
Applicant: GOOGLE LLC
Inventor： NARAYANASWAMI, Ravi
Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a circuit configured to perform computations using multiple inputs. The circuit includes multiple adder circuits and a selection circuit that includes multiple input selector. Each adder circuit performs an addition operation using sets of inputs derived from the multiple inputs. The input selectors are configured to select one or more inputs from a set of inputs derived from the multiple inputs based on a sign bit for an input in the set and pass the selected inputs to an adder circuit that generates a sum using the selected inputs. The circuit determines a routing of the sum to another adder circuit based in part on a sign bit for the input in the set of inputs.
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9.发明申请FIXED-POINT AND FLOATING-POINT ARITHMETIC OPERATOR CIRCUITS IN SPECIALIZED PROCESSING BLOCKS 审中-公开专用加工块中的固定点和浮点算术运算电路
公开(公告)号：WO2017192243A2
公开(公告)日：2017-11-09
申请号：PCT/US2017/026910
申请日：2017-04-11
Applicant: ALTERA CORPORATION
Inventor： LANGHAMMER, Martin
Abstract: The present embodiments relate to circuitry that efficiently performs floating-point arithmetic operations and fixed-point arithmetic operations. Such circuitry may be implemented in specialized processing blocks. If desired, the specialized processing blocks may include configurable interconnect circuitry to support a variety of different use modes. For example, the specialized processing block may efficiently perform a fixed-point or floating-point addition operation or a portion thereof, a fixed-point or floating-point multiplication operation or a portion thereof, a fixed-point or floating-point multiply-add operation or a portion thereof, just to name a few. In some embodiments, two or more specialized processing blocks may be arranged in a cascade chain and perform together more complex operations such as a recursive mode dot product of two vectors of floating-point numbers or a Radix-2 Butterfly circuit, just to name a few.
Abstract translation: 本发明实施例涉及有效执行浮点算术运算和定点算术运算的电路。 这种电路可以用专门的处理模块来实现。 如果需要，专用处理模块可以包括可配置互连电路以支持各种不同的使用模式。 例如，专用处理块可以高效地执行定点或浮点加法操作或其一部分，定点或浮点乘法操作或其一部分，定点或浮点乘法操作， 添加操作或其中的一部分，仅举几例。 在一些实施例中，两个或更多个专用处理块可以被布置在级联链中并且一起执行更复杂的操作，诸如浮点数的两个向量或基数2蝶形电路的递归模式点积，仅仅是为了命名 少。
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10.发明申请INSTRUCTION AND LOGIC TO PERFORM A VECTOR SATURATED DOUBLEWORD/QUADWORD ADD 审中-公开指令和逻辑执行矢量饱和的双重字/ QUADWORD ADD
公开(公告)号：WO2016105771A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/062112
申请日：2015-11-23
Applicant: INTEL CORPORATION
Inventor： OULD-AHMED-VALL, Elmoustapha , VALENTINE, Robert , TOLL, Bret L. , CORBAL SAN ADRIAN, Jesus , CHARNEY, Mark J. , GIRKAR, Milind B.
CPC classification number: G06F9/30036 , G06F7/00 , G06F9/3001 , G06F9/30018
Abstract: In several embodiments, vector extensions to an instruction set architecture include instructions to perform saturated signed and unsigned integer additions. In one embodiment, a vector signed integer add with signed saturation is provided. In one embodiment, a vector unsigned integer add with unsigned saturation is provided. In one embodiment, packed doubleword and quadword integers are supported for both signed and unsigned instructions.
Abstract translation: 在几个实施例中，指令集架构的向量扩展包括执行饱和有符号和无符号整数加法的指令。 在一个实施例中，提供了带符号饱和的向量有符号整数加法。 在一个实施例中，提供了具有无符号饱和度的向量无符号整数加法。 在一个实施例中，带符号和无符号指令都支持打包的双字和四字整数。
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