公开(公告)号：WO2022259009A1

公开(公告)日：2022-12-15

申请号：PCT/IB2021/054942

申请日：2021-06-06

Applicant: AWADHOOT LABS OÜ

Inventor： PATANKAR, Udayan Sunil ,  KOEL, Ants ,  PATANKAR, Sunil M. ,  FLORES, Miquel E

IPC: G06F7/535

Abstract: In the present invention, the divider circuit divides two integer numbers using a novel hardware and circuit implementation technique to get the resultant quotient and the residue or remainder, based on using Modified Divisor (MDr) and variable dividend grouping based on the number of zeros canceled to achieve variable conversion time or latency and area efficiency. The number of iterations depends on the number of group dividends are formed based on the count of the number of zeros canceled while deriving Modified Divisor (MDr).

公开(公告)号：WO2016171823A1

公开(公告)日：2016-10-27

申请号：PCT/US2016/023394

申请日：2016-03-21

Applicant: QUALCOMM INCORPORATED

Inventor： DOCKSER, Kenneth Alan ,  DIBRINO, Michael Thomas ,  LALL, Pathik Sunil

IPC: G06F7/535 ,  G06F7/487 ,  G06F7/537

CPC classification number: G06F7/535 ,  G06F5/01 ,  G06F7/4873 ,  G06F7/5375 ,  G06F2205/003 ,  G06F2207/535

Abstract: Systems and methods relate to division of a dividend by a divisor, with fast result formatting. Counts of leading sign bits of the dividend and the divisor are determined. The dividend and the divisor are normalized based on their respective counts of leading sign bits to obtain a normalized dividend and a normalized divisor, respectively. An exact number of significant quotient bits of a quotient of the division, based on the normalized dividend, the normalized divisor, and the counts of leading sign bits of the dividend and divisor and used to determine a correct position of a leading bit of the quotient based on this exact number. The quotient is developed by placing the leading bit at or near the correct position and appending less significant bits to the right of the leading bit. Thus, left-shifts in each iteration and large final shifts are avoided in formatting the result.

Abstract translation: 系统和方法涉及除数的分红，并具有快速的结果格式。 确定股息和除数的前导符号位数。 除数和除数根据它们各自的前导符号位的数量进行归一化，以分别获得归一化的除数和归一化除数。 基于归一化除数，归一化除数和除数和除数的前导符号位的计数，并用于确定商的前导位的正确位置，除法的商的显着商位的精确数量 基于这个确切的数字。 通过将引导位置于或接近正确位置并将较低有效位附加到引导位的右侧来开发商。 因此，在格式化结果时避免了每次迭代中的左移和大的最终偏移。

公开(公告)号：WO2009119484A1

公开(公告)日：2009-10-01

申请号：PCT/JP2009/055619

申请日：2009-03-23

Applicant: 日本電気株式会社 ,  乾 重人

Inventor： 乾 重人

IPC: G06F7/535

CPC classification number: G06F7/535 ,  G06F2207/3896

Abstract: 　商を分配するための配線長が短い除算回路及びこれを備えた半導体集積回路並びにその製造方法を提供する。 　ビットスライス部５は、上位ビット側の演算を司る第１のビットスライス部群５ａと下位ビット側の演算を司る第２のビットスライス部群５ｂとに分割されており、第１及び第２のビットスライス部群の間に商選択回路１が配置されており、第１のビットスライス部群５ａは、上位ビットの下半分に対応するビットスライス部５と上半分に対応するビットスライス部５とが交互に、上半分に対応する分は商選択回路１側から順に、下半分に対応する分は商選択回路１とは反対側から順に配列されており、第２のビットスライス部５ｂは、下位ビットに対応するビットスライス部５が商選択回路１側から順に配列されている。

Abstract translation: 可以提供一种具有短的布线长度用于划分商的分割电路。 也可以提供使用分割电路的半导体电路及其制造方法。 位片单元（5）被分成用于管理最高有效位侧的计算的第一位片单元组（5a）和用于管理最低有效位侧的计算的第二位片单元组（5b）。 商选择电路（1）被布置在第一和第二位片单元组之间。 在第一位片单元组（5a）中，交替布置与下半部分对应的位片单元（5）和对应于最高有效位的上半部分的位片单元（5）。 对应于上半部分的部分从商选择电路（1）的侧面连续布置，而下半部分的部分从商选择电路（1）的相对侧依次布置。 在第二位片单元（5b）中，从商选择电路（1）的一侧依次布置与最低有效位对应的比特片单元（5）。

公开(公告)号：WO0195090A3

公开(公告)日：2002-04-11

申请号：PCT/US0118709

申请日：2001-06-11

Applicant: PELTON WALTER E ,  HERRIDGE K WALT

Inventor： PELTON WALTER E ,  HERRIDGE K WALT

IPC: G06F1/035 ,  G06F7/52 ,  G06F7/535

CPC classification number: G06F7/535 ,  G06F2207/5354 ,  G06F2207/5356

Abstract: The present invention provides apparatus, methods, and computer program products for non-iterative division and non-iterative reciprocal generation. In one embodiment, the present invention uses a logic network that determines the bits of the quotient of a divisor and dividend by using a non-iterative, (i.e., non trial and error) method. Further, in another embodiment, the present invention may determine the reciprocal of a number M by separating the number M into at least two numbers X, Y...Z so that M = X + Y +...+ Z. The reciprocal of M is computed according to an equation 1/M = F(X, Y...Z) or an approximation 1/M APPROX G(X, Y...Z), where the approximation gives the correct value of the inverse of M to a predetermined accuracy. In some embodiments, the apparatus uses an equation that exactly describes the reciprocal or instead, it may include one or more memories for storing look-up tables containing pre-calculated parts of the equation.

Abstract translation: 本发明提供用于非迭代分割和非迭代相互产生的装置，方法和计算机程序产品。 在一个实施例中，本发明使用逻辑网络，其通过使用非迭代（即，非试验和错误）方法来确定除数和除数的商的比特。 此外，在另一个实施例中，本发明可以通过将数M分成至少两个数X，Y ... Z来确定数M的倒数，使得M = X + Y + ... + Z。 根据等式1 / M = F（X，Y ... Z）或逼近1 / M APPROX G（X，Y ... Z）计算M的值，其中近似给出正确的逆的值 的M到预定的精度。 在一些实施例中，该装置使用精确描述倒数的方程式，或者替代地，其可以包括用于存储包含方程式的预先计算部分的查找表的一个或多个存储器。

公开(公告)号：WO99067704A1

公开(公告)日：1999-12-29

申请号：PCT/JP1999/003352

申请日：1999-06-23

IPC: G06F7/537 ,  G06F1/02 ,  G06F1/035 ,  G06F7/52 ,  G06F7/535

CPC classification number: G06F7/535 ,  G06F1/0356 ,  G06F2101/12 ,  G06F2207/5355 ,  G06F2207/5356

Abstract: A method for calculating the initial value in the Newton-Raphson method by synthesization using values retrieved from a small table stored in a memory by means of an arithmetic unit. The method of the invention is free from problems of conventional dividers such as a long operating time and a large circuit scale. The iterative calculation circuit of the Newton-Raphson method is mounted as an arithmetic circuit. A reciprocal calculating circuit having a short operating time, usable as a pipeline system, and exhibiting an improved throughput and a dividing circuit comprising the reciprocal calculating circuit are mounted. Part of the multiplying circuit included in the iterative calculation circuit is omitted by regarding the calculation precision, thus making it a compact iterative calculation circuit. Further by using the interim results of the calculation, the calculation precision is readily enhanced. Thus, a method for calculating the minimum size required for the table used for calculating the initial value is provided, and means for designing a circuit of a requisite minimum while fulfilling the required calculation precision is also provided.

Abstract translation: 一种通过使用通过算术单元存储在存储器中的小表检索的值进行合成来计算牛顿 - 拉夫逊方法中的初始值的方法。 本发明的方法没有常规分频器的问题，例如长的操作时间和大的电路规模。 牛顿 - 拉夫逊方法的迭代计算电路作为运算电路进行安装。 安装具有短的操作时间的可逆计算电路，可用作管道系统，并且具有改善的吞吐量，并且包括倒数计算电路的分频电路。 通过关于计算精度来省略包含在迭代计算电路中的乘法电路的一部分，从而使其成为紧凑的迭代计算电路。 此外，通过使用中期计算结果，可以容易地提高计算精度。 因此，提供了一种用于计算用于计算初始值的表所需的最小尺寸的方法，并且还提供了用于在满足所需的计算精度的同时设计必需最小值的电路的装置。

公开(公告)号：WO2022261605A2

公开(公告)日：2022-12-15

申请号：PCT/US2022/072707

申请日：2022-06-02

Applicant: TENCENT AMERICA LLC

Inventor： ZHANG, Xiang ,  GAO, Wen ,  LIU, Shan

IPC: G06K9/62 ,  G06T9/40 ,  G06T17/05 ,  G06T7/60 ,  G06T7/73 ,  G06T17/30 ,  H04N19/10 ,  H04N19/59 ,  H04N19/70 ,  G06F1/03 ,  G06F5/01 ,  G06F7/50 ,  G06F7/535 ,  G06T9/001

Abstract: Aspects of the disclosure provide methods and apparatuses for point cloud compression and decompression. In some examples, an apparatus for point cloud compression/decompression includes processing circuitry. The processing circuitry determines to use a prediction mode for coding (encoding/ decoding) information associated with a current point in a point cloud. In the prediction mode, the information associated with the current point is predicted based on one or more neighbor points of the current point. The processing circuitry calculates, using integer operations, a distance-based weighted average value based on distances of the one or more neighbor points to the current point, and determines the information associated with the current point based on the distance-based weighted average value.

公开(公告)号：WO2006128076A2

公开(公告)日：2006-11-30

申请号：PCT/US2006/020637

申请日：2006-05-25

Applicant: QUALCOMM INCORPORATED ,  XIAO, Shu ,  DU, Junchen ,  SHEN, Tao

Inventor： XIAO, Shu ,  DU, Junchen ,  SHEN, Tao

IPC: H04N7/26 ,  G06F7/535 ,  G06F7/487 ,  H04N7/50

CPC classification number: H04N19/18 ,  G06F7/4873 ,  G06F7/49963 ,  G06F7/535 ,  G06F2101/12 ,  G06F2207/5356 ,  H04N19/42 ,  H04N19/593 ,  H04N19/61

Abstract: The disclosure describes a method for performing a fixed point calculation of a floating point operation (A // B) in a coding device, wherein A // B represents integer division of A divided by B rounded to a nearest integer. The method may comprise selecting an entry from a lookup table (LUT) having entries generated as an inverse function of an index B, wherein B defines a range of values that includes every DC scalar value and every quantization parameter associated with a coding standard, and calculating A // B for coding according to the coding standard based on values A, B1 and B2, wherein B1 and B2 comprise high and low portions of the selected entry of the LUT. The techniques may simplify digital signal processor (DSP) implementations of video coders, and are specifically useful for MPEG-4 coders and possibly others.

Abstract translation: 本公开描述了一种用于在编码装置中执行浮点运算（A // B）的固定点计算的方法，其中A // B表示A除以被舍入为最接近整数的B的整数除法。 该方法可以包括从具有作为索引B的反函数生成的条目的查找表（LUT）中选择条目，其中B定义包括每个DC标量值和与编码标准相关联的每个量化参数的值的范围，以及 基于值A，B1和B2，根据编码标准计算A // B进行编码，其中B1和B2包括LUT的所选条目的高和低部分。 这些技术可以简化视频编码器的数字信号处理器（DSP）实现，并且对MPEG-4编码器和可能的其它编码器特别有用。

公开(公告)号：WO9953416A3

公开(公告)日：2003-04-17

申请号：PCT/US9904300

申请日：1999-04-09

Applicant: LOCKHEED CORP

Inventor： MEEKER WOODROW L ,  VAN DYKE-LEWIS MICHELE D

IPC: G06F7/02 ,  G06F7/52 ,  G06F7/535

CPC classification number: G06F7/535 ,  G06F7/02

Abstract: Methods and apparatus for quickly dividing multiple-bit operands using bit-serial processors include strategies for eliminating the number of steps required to execute conventional division operations. According to an exemplary embodiment, a conditional subtraction step, based on a quotient bit computed during a given pass, is combined with a compare step which is used to compute a next quotient bit and which, according to conventional techniques, is ordinarily computed during a subsequent pass. Additionally, exemplary embodiments provide a zero/non-zero mask for denominator bits which extend beyond current most signficant remainder bit during a given pass. As a result, not all denominator bits need be considered during every pass. Advantageously, the methods and apparatus of the invention can provide approximately a 3 to 1 speed improvement as compared to conventional techniques.

Abstract translation: 使用位串行处理器快速分割多位操作数的方法和装置包括消除执行常规分割操作所需步骤数量的策略。 根据示例性实施例，基于在给定通过期间计算的商位的条件减法步骤与用于计算下一个商位的比较步骤组合，并且根据常规技术通常在 随后通过。 另外，示例性实施例为给定通过期间延伸超过当前最重要的余数位的分母位提供零/非零掩模。 因此，在每次通过期间都不需要考虑所有的分母比特。 有利地，与常规技术相比，本发明的方法和设备可以提供大约3比1的速度改进。

公开(公告)号：WO0045253A9

公开(公告)日：2002-05-02

申请号：PCT/US0001780

申请日：2000-01-24

Applicant: SUN MICROSYSTEMS INC

Inventor： SHANKAR RAVI ,  SUDHARSANAN SUBRAMANIA I

IPC: G06F7/499 ,  G06F7/52 ,  G06F7/535 ,  G06F9/302

CPC classification number: G06F7/535 ,  G06F7/4873 ,  G06F7/49947 ,  G06F7/49957 ,  G06F7/49963 ,  G06F9/30014 ,  G06F2207/3884

Abstract: A computation unit computes a division operation Y/X by determining the value of a divisir reciprocal l/X and multiplying the reciprocal by a numerator Y. The reciprocal l/X value is determined using a quadratic approximation having a form: Ax +Bx+C, where coefficients A, B, and C are constants that are stored in a storage or memory such as a read-only memory (ROM). The bit length of the coefficient determines the error in a final result. Storage size is reduced through use of "least mean square error" techniques in the determination of the coefficients that are stored in the coefficient storage. During the generation of partial products x , Ax , and Bx, the process of rounding is eliminated, thereby reducing the computational logic to implement the division functionality.

Abstract translation: 计算单元通过确定二进制倒数l / X的值并将倒数乘以分子Y来计算除法运算Y / X。使用具有以下形式的二次近似来确定倒数l / X值：Ax <2> + Bx + C，其中系数A，B和C是存储在诸如只读存储器（ROM）的存储器或存储器中的常数。 系数的位长决定最终结果中的误差。 在确定系数存储器中存储的系数时，通过使用“最小均方误差”技术来减少存储大小。 在部分乘积x 2，Ax 2和B x的产生期间，舍入的过程被消除，从而减少了实现分割功能的计算逻辑。

公开(公告)号：WO02029546A1

公开(公告)日：2002-04-11

申请号：PCT/JP2000/006612

申请日：2000-09-26

IPC: G06F7/52 ,  G06F7/535 ,  G06F7/552

CPC classification number: G06F7/535 ,  G06F7/483 ,  G06F7/4873 ,  G06F7/5375 ,  G06F7/5525 ,  G06F2207/382 ,  G06F2207/5528

Abstract: A single-/double-precision selector (106), a CPA (107) for performing a carry-propagation of a partial remainder, a quotient digit selection circuit (108) and a divisor selector (109) are added to the low-order side of a double-precision-bit-width SRT floating-point divider, a selector for selecting a carry propagation is provided between CSAs on the high-order and low-order sides, and a start position selector is provided within a quotient generating circuit, thereby it is possible to simultaneously execute two computations of a single-precision division without increasing the width of a computing unit. Since, during a double-precision computation, the same inputs are given to the quotient digit selection circuit to double the drive force of a selected quotient digit, a faster circuit can be implemented during a double-precision computation. As for a square-root computation, a single-precision two-computation parallel execution is possible just as is the case with division by adding a partial square root circuit.

Abstract translation: 用于执行部分余数的进位传播的单/双精度选择器（106），CPA（107），商数选择电路（108）和除数选择器（109）被加到低位 在双精度位宽SRT浮点除法器的一侧，在高阶和低阶侧的CSA之间提供用于选择进位传播的选择器，并且在商发生电路内提供起始位置选择器 ，从而可以在不增加计算单元的宽度的情况下同时执行单精度分割的两次计算。 由于在双精度计算中，相同的输入被赋予商数选择电路以将所选商数的驱动力加倍，所以可以在双精度计算期间实现更快的电路。 对于平方根计算，单精度双计算并行执行是可能的，就像通过添加部分平方根电路进行除法的情况一样。