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公开(公告)号:WO2021151112A1
公开(公告)日:2021-07-29
申请号:PCT/US2021/070057
申请日:2021-01-21
Applicant: BRIGHTLOGIC, INC.
Inventor: SCARPA, John, D. , CHAMBERS, Mark
IPC: G06F3/041 , G06F3/042 , G09G3/32 , G09G3/3225 , G09G5/00 , G09G2300/0842 , G09G2360/141 , H01L33/486 , H05B47/195
Abstract: Disclosed embodiments provide an LED package and electronic display. An LED package can include an LED that emits red, green, blue and IR (infrared), where the IR portion is configured as either an emitter or (reversed biased) as a receiver. An electronic display includes multiple LED packages with the IR portions configured in a combination of transmitters and receivers. Thus, disclosed embodiments enable electronic displays that can serve as interactive video walls and floors that present a high-definition image along with interactive capabilities. Thus, disclosed embodiments serve to reduce cost and complexity in manufacture and deployment of such displays.
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公开(公告)号:WO2022200863A2
公开(公告)日:2022-09-29
申请号:PCT/IB2022/000186
申请日:2022-03-26
Applicant: FORTH DIMENSION DISPLAYS, LTD
Inventor: CHALMERS, Christopher, Robert
IPC: G09G3/32 , G09G2300/0842 , G09G2300/0857 , G09G2300/0861 , G09G2310/0251 , G09G2310/0259 , G09G2310/027 , G09G2310/0291 , G09G2310/08 , G09G2320/0233 , G09G2320/0276 , G09G3/2018 , G09G3/2074
Abstract: Method, apparatuses, and systems are described to display image data to a sub- pixel within a micro-LED (mLED) display. A sub-pixel image data value is stored at the sub-pixel. The sub-pixel is turned to an ON state. A shared row counter value Is provided to the sub-pixel, The shared row counter value and the sub-pixel image data value are compared at the sub-pixel. The sub-pixel is turned to an OFF state if the shared row counter value is equal to or greater than the sub-pixel image data value.
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公开(公告)号:WO2021189323A1
公开(公告)日:2021-09-30
申请号:PCT/CN2020/081195
申请日:2020-03-25
Applicant: 京东方科技集团股份有限公司 , 成都京东方光电科技有限公司
IPC: H01L27/32 , H01L21/77 , G09G3/32 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/061 , G09G3/3233 , G09G3/3275 , H01L27/3248 , H01L27/326 , H01L27/3276
Abstract: 一种显示面板及其制作方法、显示装置。显示面板包括:多个子像素区,以及位于各子像素区中的复位信号线图形(905)、初始化信号线图形(904)和导电连接部图形(909);初始化信号线图形(904)包括相耦接的第一主体部分(9041)和第一突出部分(9042),第一主体部分(9041)在基底上的正投影位于第一突出部分(9042)在基底上的正投影与复位信号线图形(905)在基底上的正投影之间;导电连接部图形(909)的第一端部(9091)在基底上的正投影,与第一突出部分(9042)在基底上的正投影具有第一交叠区域(F1),在第一交叠区域(F1),第一端部(9091)与第一突出部分(9042)耦接,导电连接部图形(909)的第二端部(9092)与目标耦接部耦接,复位信号线图形(905)在基底上的正投影,位于目标耦接部在基底上的正投影与初始化信号线图形(904)在基底上的正投影之间。
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公开(公告)号:WO2023277611A1
公开(公告)日:2023-01-05
申请号:PCT/KR2022/009417
申请日:2022-06-30
Applicant: 삼성디스플레이 주식회사
IPC: G09G3/32 , H01L27/12 , G09G2300/0408 , G09G2300/0842 , G09G3/3266
Abstract: 표시 장치는 복수의 스캔선 및 복수의 데이터선에 각각 전기적으로 연결된 화소들; 상기 복수의 스캔선들 각각에 스캔 신호를 제공하는 스캔 구동부; 제1 게이트 전원 배선을 통해 제1 게이트 전압을 상기 스캔 구동부에 공급하는 전압 공급부; 및 전압 보상부를 포함한다. 상기 전압 보상부는 피드백 배선을 통해 상기 스캔 구동부에 인가된 상기 제1 게이트 전압 중 일부 전압을 센싱한다. 상기 전압 보상부는 제1 기준 전압보다 센싱된 전압이 큰 경우에 상기 제1 게이트 전압을 제2 게이트 전압으로 보상한다.
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公开(公告)号:WO2021133461A1
公开(公告)日:2021-07-01
申请号:PCT/US2020/057574
申请日:2020-10-27
Applicant: APPLE INC.
Inventor: LIN, Chin-Wei , ONO, Shinya , HUANG, Jung Yen
IPC: G09G3/3233 , H01L27/12 , G09G2300/0417 , G09G2300/0465 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/0256 , G09G2320/0209 , G09G2320/0238 , G09G2320/0247 , G09G3/2092 , G09G3/3266 , G09G3/3291 , H01L27/1225 , H01L27/1251 , H01L27/1255
Abstract: A display pixel may include an organic light-emitting diode, one or more emission transistors, a drive transistor, a gate setting transistor, a data loading transistor, and an initialization transistor. The drive transistor may be implemented as a semiconducting-oxide transistor to mitigate threshold voltage hysteresis to improve first frame response at high refresh rates, to reduce undesired luminance jumps at low refresh rates, and to reduce image sticking. The gate setting transistor may also be implemented as a semiconducting-oxide transistor to reduce leakage at the gate terminal of the drive transistor. The initialization transistor may also be implemented as a semiconducting-oxide transistor so that it can be controlled using a shared emission signal to reduce routing complexity. The remaining transistors in the pixel may be implemented as p-type silicon transistors. Display pixels configured in this way can support in-pixel threshold voltage compensation and on-bias stress phase to further mitigate the hysteresis.
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公开(公告)号:WO2022188374A1
公开(公告)日:2022-09-15
申请号:PCT/CN2021/115249
申请日:2021-08-30
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: FENG, Yu , LIU, Libin , LU, Jiangnan
IPC: G09G3/3233 , H01L27/32 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842 , G09G2310/0251 , H01L27/3262 , H01L27/3265 , H01L27/3276
Abstract: An array substrate is provided. A respective pixel driving circuit of the array substrate includes a driving transistor, a storage capacitor, and a transistor having a gate electrode connected to a respective second gate line of a plurality of second gate lines, a first electrode connected to a first capacitor electrode of the storage capacitor, and a second electrode connected to a second electrode of a first reset transistor, the transistor being configured to receive a reset signal through the first reset transistor. An active layer of the driving transistor and an active layer of the transistor are spaced apart from each other by at least an insulating layer. The active layer of the driving transistor comprises a first semiconductor material. The active layer of the transistor comprises a second semiconductor material different from the first semiconductor material.
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公开(公告)号:WO2021104481A1
公开(公告)日:2021-06-03
申请号:PCT/CN2020/132389
申请日:2020-11-27
Applicant: 京东方科技集团股份有限公司 , 成都京东方光电科技有限公司
IPC: H01L27/12 , G09G3/3225 , H01L27/32 , G09G2300/0426 , G09G2300/0842 , G09G3/3233 , H01L27/3262 , H01L27/3265 , H01L27/3272 , H01L27/3276
Abstract: 一种显示基板和显示装置,显示基板包括基底(50)和在基底(50)上阵列分布的多个子像素;子像素包括:沿第一方向(Y)延伸的数据线图形(DATA1,DATA2);包括沿第一方向(Y)延伸的部分的电源信号线图形(VDD);以及子像素驱动电路,子像素驱动电路包括:两个开关晶体管(T4、T5)、驱动晶体管(T3)和存储电容(Cst);存储电容(Cst)的第一极板(Cst1)与驱动晶体管(T3)的栅极(203g)耦接,存储电容(Cst)的第二极板(Cst2)与电源信号线图形(VDD)耦接;两个开关晶体管(T4、T5)的第二极(D4、D5)均与驱动晶体管(T3)的第一极(S3)耦接,两个开关晶体管(T4、T5)中的至少一个开关晶体管(T4、T5)的第二极(D4、D5)在基底(50)上的正投影,与电源信号线图形(VDD)在基底(50)上的正投影至少部分重叠,且与存储电容(Cst)的第二极板(Cst2)在基底(50)上的正投影至少部分重叠。
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