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公开(公告)号：WO2023091067A1
公开(公告)日：2023-05-25
申请号：PCT/SE2022/051067
申请日：2022-11-15
申请人： BEAMMWAVE AB
摘要： A method (100) for a processor (600), the processor (600) being connectable to a plurality of transceivers (500, …, 508) via one or more digital interfaces (400, …, 408), comprising: configuring (110) a first set of the plurality of transceivers (500, …, 508) to be in a first operating mode for a first time period; configuring (120) a second set of the plurality of transceivers (500, …, 508) to be in a non-operating mode for the first time period; configuring (130) the second set of transceivers to be in a second operating mode for a second time period, the second time period following the first time period; during the second time period obtaining (140) a signal quality/strength for each of the plurality of transceivers (500, …, 508); and at the end of the second time period, updating (150) the first and second sets of transceivers based on the obtained signal quality/strength. Corresponding computer program product, apparatus and digital interface are also disclosed.
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公开(公告)号：WO2022262995A1
公开(公告)日：2022-12-22
申请号：PCT/EP2021/066599
申请日：2021-06-18
发明人： SJÖLAND, Henrik
摘要： A multi-carrier transceiver receives and transmits wireless communication signals on multiple carriers simultaneously. To generate Local Oscillator (LO) signals for mixers operating at different frequencies, a multi-frequency LO signal generating circuit includes a set of integer-N Phase Locked Loop (PLL) circuits. All PLL circuits receive the same reference frequency, but output different frequency LO signals, each at an integer multiple of the reference frequency. The LO signal frequencies are thus on an equidistant frequency grid having a granularity of the reference frequency. Spurs are also at multiples of the reference frequency, and can be easily filtered. A fractional-N PLL circuit may generate the reference frequency, making the frequency grid adjustable. A plurality of the PLL circuits in the set output a phase error feedback signal to a phase error correction circuit, and receive a phase error control signal that phase-locks the plurality of PLL circuits together and mitigates phase noise deviations between them. PLL circuits operating near a transmitter frequency are not in the phase-locked plurality, so all PLL circuits are not frequency pulled. Complex channel select filters are used for carriers not aligned with a LO signal.
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3.发明申请
公开(公告)号：WO2022165021A1
公开(公告)日：2022-08-04
申请号：PCT/US2022/014079
申请日：2022-01-27
发明人： HWANG, Sewook
IPC分类号： H03L7/08
摘要： Aspects of the technology described herein relate to an ultrasound device that may has a phase-locked loop (PLL) that includes a digitally-controlled oscillator (DCO). The DCO includes a plurality of current source unit cells with respective drain switches a plurality of current source unit cells with respective source switches. The plurality of current source unit cells with respective drain switches and the plurality of current source unit cells may have different circuit topologies. Switching on one of the plurality of current source unit cells with respective drain switches may cause a voltage transition at an internal node proceeding in one voltage direction and switching on one of the plurality of current source unit cells with respective source switches may cause a voltage transition at an internal node proceeding in the opposite voltage direction.
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公开(公告)号：WO2022080947A1
公开(公告)日：2022-04-21
申请号：PCT/KR2021/014357
申请日：2021-10-15
申请人： 삼성전자 주식회사
发明人： 양성기
摘要： 본 개시는 LTE(long term evolution)와 같은 4G(4th generation) 통신 시스템 이후 보다 높은 데이터 전송률을 지원하기 위한 5G(5th generation) 또는 pre-5G 통신 시스템을 IoT 기술과 융합하는 통신 기법 및 그 시스템에 관한 것이다. 본 개시는 5G 통신 기술 및 IoT 관련 기술을 기반으로 지능형 서비스 (예를 들어, 스마트 홈, 스마트 빌딩, 스마트 시티, 스마트 카 혹은 커넥티드 카, 헬스 케어, 디지털 교육, 소매업, 보안 및 안전 관련 서비스 등)에 적용될 수 있다. 본 개시의 다양한 실시 예들에 따라 무선 통신 시스템에서 다수의 사업자를 지원하는 네트워크 공유 방법 및 장치 제공할 수 있다.
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公开(公告)号：WO2022060887A1
公开(公告)日：2022-03-24
申请号：PCT/US2021/050530
申请日：2021-09-15
发明人： HAJIMIRI, Seyed Ali
IPC分类号： H04B10/54 , H04B10/516 , H04B10/572 , H03L7/08 , G02B6/42 , G02B6/28
摘要： A system includes, in part, a first optical modulator adapted to modulate a first optical signal with a first data to generate a first modulated optical signal, a second optical modulator adapted to modulate a second optical signal with a first clock signal to generate a second modulated optical signal, an optical multiplexer adapted to multiplex the first and second optical signals to generate a multiplexed optical signal, and an optical fiber adapted to carry the multiplexed optical signal. The second optical signal has a second wavelength that is different from the first wavelength.
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公开(公告)号：WO2022041277A1
公开(公告)日：2022-03-03
申请号：PCT/CN2020/112728
申请日：2020-08-31
申请人： 华为技术有限公司
IPC分类号： H03L7/08
摘要： 一种锁相环（10）和射频收发机，涉及无线通信领域，用于降低除法器（35）和电荷泵（32）的噪声，降低工作在小数频点的锁相环（10）的相位噪声。锁相环（10）包括：相位检测器（31）、电荷泵（32）、低通滤波器（33）、压控振荡器（34）和除法器（35）；压控振荡器（34）输出振荡信号；除法器（35）接收振荡信号，输出第一分频信号（DIV1）和第二分频信号（DIV2）；相位检测器（31）接收参考信号（REF）、第一分频信号（DIV1）和第二分频信号（DIV2），基于第一分频信号（DIV1）和第二分频信号（DIV2）中的一个以及参考信号（REF），输出电荷泵控制信号；电荷泵（32）包括耦合于电荷泵（32）的输出端的可变电流源（A0）和并联的第一电流源单元（321）；第一电流源单元（321）包括串联的固定电流源（A1-AM）和开关（K1-KM），可变电流源（A0）接收偏移控制信号，偏移控制信号用于调节可变电流源（A0）的电流大小；电荷泵控制信号用于控制第一电流源单元（321）的开关（K1-KM）的通断；低通滤波器（33）用于过滤电荷泵（32）的输出电流后输出给压控振荡器（34）。
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公开(公告)号：WO2021233203A1
公开(公告)日：2021-11-25
申请号：PCT/CN2021/093649
申请日：2021-05-13
申请人： 中兴通讯股份有限公司
发明人： 赵亮
摘要： 一种相位检测方法及其装置、设备。其中，相位检测装置包括信号处理组件、鉴相部件和相位比较组件，信号处理组件被设置成获取参考时钟信号及其初始相位值；鉴相部件被设置成获取待测时钟信号，并根据参考时钟信号和待测时钟信号得到第一相位差信号；相位比较组件被设置成根据第一相位差信号得到相位调整信号；此外，信号处理组件还被设置成根据相位调整信号对参考时钟信号进行相位调整，以减小第一相位差信号，并累计调整的相位值以得到相位累计值，且根据相位累计值和初始相位值得到待测时钟信号的相位值。
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公开(公告)号：WO2021035229A2
公开(公告)日：2021-02-25
申请号：PCT/US2020/063156
申请日：2020-12-03
申请人： ZEKU, INC.
发明人： TOOSIZADEH, Navid , ZHANG, Yu
摘要： Embodiments of the disclosure provide a voltage / frequency modulation (VFM) system for determining a baseline voltage and a programmable ring oscillator (PRO) code for various dynamic voltage frequency scaling (DVFS) set points. The VFM system may include, e.g., a memory and at least one processor coupled to the memory. In certain aspects, the at least one processor may determine, for each of a plurality of DVFS set points, a lowest voltage at which a workload is performed at a subsystem. The at least one processor may program a voltage regulator with the lowest voltage for each DVFS set point. In certain other aspects, the at least one processor may determine a PRO code (e.g., coarse delay code and fine delay code) associated with a PRO at the lowest voltage. The PRO code may match a predetermined phase-locked loop (PEL) frequency to within a threshold. In still other aspects, the at least one processor may maintain the PRO code in a register.
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9.发明申请
公开(公告)号：WO2021029959A1
公开(公告)日：2021-02-18
申请号：PCT/US2020/037770
申请日：2020-06-15
摘要： A method and corresponding system of determining a property of a particle, comprising: flowing the particle in a device comprising a suspended microchannel resonator, the suspended microchannel resonator comprising a microfluidic channel configured to receive the plurality of particles; driving the suspended microchannel resonators with an excitation element; sensing a resonance frequency of the suspended microchannel resonators as the particle flows in the microfluidic channel; and modifying the resonance frequency of the suspend microchannel resonator to determine the property of the particle.
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公开(公告)号：WO2020244158A1
公开(公告)日：2020-12-10
申请号：PCT/CN2019/118687
申请日：2019-11-15
发明人： EMIRA, Ahmed , HUSSIEN, Faisal
IPC分类号： H03L7/08
摘要： A fractional divider in modulated phase-lock loop circuits. The fractional divider can receive a base dividing value having integer and fractional components, and can also receive a data signal to modulate the dividing value. A shift value is used to selectively shift and scale the modulated dividing value to generate a shifted fractional component value. The shifted fractional component value can be added to the base integer component, and de-shifted and de-scaled to generate a corrected dividing value. A feedback signal can then be generated by sequentially dividing a frequency of a clock output signal by the corrected dividing value.
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