US09570742B2
Provided is a secondary battery comprising a positive electrode active material represented by the following Chemical Formula 1, Li{LiaMnxM1-a-x-yM′y}O2 [Chemical Formula 1] where 0
(1−a)/2, and 0
US09570731B2
A rechargeable battery includes an electrode assembly including a first electrode, a second electrode, and a separator located between the first electrode and the second electrode; a case accommodating the electrode assembly; a cap plate sealing an opening of the case; and an insulation case located between the cap plate and the electrode assembly, the insulation case having a base and a side wall protruding from the base, the side wall including avoiding portions formed thereon.
US09570730B2
A bridge power connector includes upper and lower connector assemblies. The upper connector assembly has an upper housing holding an upper power conductor connected to a first electrical component. The lower connector assembly has a lower housing holding a lower power conductor electrically connected to a second electrical component. The upper housing is removably coupled to the lower housing using securing mechanisms to form a low-profile housing. The upper power conductor extends from a first side of the low-profile housing while the lower power conductor extends from a second side of the low-profile housing. The upper and lower power conductors extend along a mating plane of the low-profile housing. The upper power conductor is separable from the lower power conductor when the upper housing is removed from the lower housing.
US09570719B2
A secondary battery includes an electrode assembly; a case accommodating the electrode assembly; a cap plate sealing the electrode assembly within the case; a terminal plate on the cap plate and electrically connected to the electrode assembly; and an insulation member between and contacting the cap plate and the terminal plate, wherein the insulation member has a peripheral flange that extends away from the terminal plate.
US09570718B2
A packaging material for batteries, which is formed of a laminate that sequentially includes a base layer, an adhesive layer, a barrier layer and a sealant layer in this order. By having the adhesive layer formed of a cured product of a resin composition that contains a thermosetting resin and (A) a curing accelerator and an elastomer resin or (B) reactive resin beads, the adhesive layer arranged between the base layer and the barrier layer can be cured in a short time, thereby reducing the lead time. In addition, by providing the adhesive layer between the base layer and the barrier layer, the adhesion strength between the base layer and the barrier layer is increased and excellent formability can be achieved.
US09570704B2
A display device includes a first substrate, a second substrate, a connecting element and a display medium. The first and second substrates are disposed opposite to each other, and the connecting element is disposed between the first and second substrates. An accommodating space is formed between the first substrate, the second substrate and the connecting element, and the display medium is disposed in the accommodating space. The connecting element has a first sealing layer, a second sealing layer and an adhesive layer. The first and second sealing layers are departed or partially connected. The second sealing layer is disposed adjacent to the accommodating space. The adhesive layer is disposed between the first and second sealing layers. The adhesive layer includes a water-resisting material.
US09570685B2
A method includes forming an emission pattern on an organic electroluminescent element including an organic functional layer between two electrodes by light irradiation to the organic electroluminescent element, and controlling at least one of light intensity and exposure time as variable factors during the light irradiation based on reciprocity failure characteristics involving modification of a function of the organic functional layer due to the light irradiation.
US09570684B2
Example embodiments relate to methods of doping a 2-dimensional semiconductor. The method includes forming a semiconductor layer on a substrate, implanting ions into the semiconductor layer, forming a doped layer formed of a 2-dimensional semiconductor layer or an organic semiconductor layer on the semiconductor layer, and doping the doped layer by diffusing the ions of the semiconductor layer into the doped layer through annealing the substrate.
US09570678B1
A non-volatile memory device includes a first dielectric on a substrate, a first electrode disposed on the first dielectric, a second dielectric material disposed next to the first electrode, a patterned material disposed upon the second dielectric material and in contact with part of the first electrode, a third dielectric material disposed next to the patterned material and in contact with another part of the first electrode, wherein the patterned material and the third dielectric material contact at an interface region, wherein the interface region is characterized by a plurality of defects, a second electrode disposed on the patterned material, on the third dielectric, and on the interface region, wherein the second electrode comprises metal particles that are configured to be diffused within the interface region upon application of a bias voltage, and wherein metal particles are disposed within the plurality of defects in the interface region.
US09570677B2
Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material. Some embodiments include a method of forming a memory cell. Chalcogenide material may be formed over heater material. Electrically conductive material may be formed over the chalcogenide material. A thermal sink may be formed between the electrically conductive material and the chalcogenide material. The thermal sink may be of a composition that includes an element in common with the electrically conductive material and includes an element in common with the chalcogenide material.
US09570676B2
In the method of manufacturing a magnetoresistive sensor module, at first a composite arrangement out of a semiconductor substrate and a metal-insulator arrangement is provided, wherein a semiconductor circuit arrangement is integrated adjacent to a main surface of the semiconductor substrate into the same, wherein the metal-insulator arrangement is arranged on the main surface of the semiconductor substrate and comprises a structured metal sheet and insulation material at least partially surrounding the structured metal sheet, wherein the structured metal sheet is electrically connected to the semiconductor circuit arrangement. Then, a magnetoresistive sensor structure is applied onto a surface of the insulation material of the composite arrangement, and finally an electrical connection between the magnetoresistive sensor structure and the structured metal sheet is established, so that the magnetoresistive sensor structure is connected to the integrated circuit arrangement.
US09570675B2
Magnetoresistive structures, magnetic random-access memory devices including the same, and methods of manufacturing the magnetoresistive structure, include a first magnetic layer having a magnetization direction that is fixed, a second magnetic layer corresponding to the first magnetic layer, wherein a magnetization direction of the second magnetic layer is changeable, and a magnetoresistance (MR) enhancing layer and an intermediate layer both between the first magnetic layer and the second magnetic layer.
US09570671B2
According to one embodiment, a magnetic memory device includes a stacked structure including a magnetic element, a protective insulating film covering the stacked structure, and an interface layer provided at an interface between the stacked structure and the protective insulating film. The interface layer contains a predetermined element which is not contained in the magnetic element or the protective insulating film.
US09570668B2
In a method for manufacturing a piezoelectric device while stably achieving strong bonding, a moisture-absorbing layer is formed on a bonding surface side of a piezoelectric single-crystal substrate. The moisture-absorbing layer is allowed to absorb moisture. A binder layer is formed on a bonding surface side of a supporting substrate. The moisture-absorbing layer is placed on the binder layer. A silica precursor in the binder layer is converted into silica through a hydrolysis reaction with moisture in the moisture-absorbing layer.
US09570667B2
According to an embodiment, a thermoelectric conversion material is made of a polycrystalline material which is represented by a composition formula (1) shown below and has a MgAgAs type crystal structure. The polycrystalline material includes a MgAgAs type crystal grain having regions of different Ti concentrations. (AaTib)cDdXe Composition formula (1) wherein 0.2≦a≦0.7, 0.3≦b≦0.8, a+b=1, 0.93≦c≦1.08, and 0.93≦e≦1.08 hold when d=1; A is at least one element selected from the group consisting of Zr and Hf, D is at least one element selected from the group consisting of Ni, Co, and Fe, and X is at least one element selected from the group consisting of Sn and Sb.
US09570666B2
Various embodiments of a thermal energy transfer apparatus that removes thermal energy from a light-emitting device are described. In one aspect, an apparatus comprises a non-metal base plate and a silicon-based cover element disposed on the base plate. The base plate is coated with a first electrically-conductive pattern that forms a first electrode. The base plate is further coated with a second electrically-conductive pattern that is electrically isolated from the first electrically-conductive pattern. The cover element holds the one or more light-emitting devices between the base plate and the cover element with at least a portion of a light-emitting surface of each of the one or more light-emitting devices exposed. The cover element is coated with a third electrically-conductive pattern that is in contact with the second electrically-conductive pattern to form a second electrode when the cover element is disposed on the base plate.
US09570660B2
Provided is a semiconductor light emitting device. The semiconductor light emitting device may include: a light emitting structure comprising a first conductivity-type semiconductor layer having an upper surface divided into first and second regions, an active layer and a second conductivity-type semiconductor layer sequentially disposed on the second region of the first conductivity-type semiconductor layer; a first contact electrode disposed on the first region of the first conductivity-type semiconductor layer; a second contact electrode disposed on the second conductivity-type semiconductor layer; a first electrode pad electrically connected to the first contact electrode and having at least a portion disposed on the second contact electrode; a second electrode pad electrically connected to the second contact electrode; and a multilayer reflective structure interposed between the first electrode pad and the second contact electrode and comprising a plurality of dielectric layers which have different refractive indices and are alternately stacked.
US09570658B2
To provide a semiconductor light emitting element with high luminous efficiency, the light emitting element includes: a substrate; a semiconductor laminate placed above the substrate, the semiconductor laminate comprising a second semiconductor layer, an active layer and a first semiconductor layer laminated in this order from the substrate; and a first electrode and a second electrode placed between the substrate and the semiconductor laminate, wherein the semiconductor laminate is divided in a plurality of semiconductor blocks by a groove, wherein the first electrode includes protrusions that are provided in each of the plurality of semiconductor blocks and that penetrate the second semiconductor layer and the active layer to be connected to the first semiconductor layer, and wherein the second electrode is connected to the second semiconductor layer in each of the plurality of semiconductor blocks and has an external connector that is exposed on the bottom of the groove.
US09570653B2
A method for fabricating a light-emitting device is provided. The method includes: providing a substrate; forming a sacrificial dielectric layer on the substrate, wherein the sacrificial dielectric layer is a structure containing voids; forming a buffer layer on the sacrificial dielectric layer; forming an epitaxial light-emitting structure on the buffer layer; forming a metal bonding layer on the epitaxial light-emitting structure; bonding the metal bonding layer to a thermally conductive substrate; and wet etching the sacrificial dielectric layer for to remove the substrate.
US09570642B2
Provided is a sealing material sheet for solar cell modules, which is obtained by irradiating a polyethylene resin with ionizing radiation and has high transparency, heat resistance and adhesion at the same time. This sealing material sheet for solar cell modules contains a low density polyethylene having a density of 0.900 g/cm3 or less, while having a gel fraction of from 0% to 40% (inclusive) and a degree of dispersity (Mw/Mn), which is the ratio of the weight average molecular weight (Mw) to the number average molecular weight (Mn) in terms of polystyrene, of from 2.5 to 3.5 (inclusive).
US09570641B2
Provided is a polymer from which an encapsulant excellent in weather resistance and processability can be obtained when being used for an encapsulant for a solar cell. The polymer that has a main chain comprising repeating units represented by formula (1) and repeating units represented by formula (2) and satisfies requirements (a1), (a2), and (a3), (a1): the ratio of the number of the repeating units represented by formula (2) to the total number of the carbon atoms that constitute the main chain of the polymer is from 3.8% to 7.5%; (a2): the ratio X represented by formula (3) is from 82% to 100%; X=100×A/B (3) (a3): the polymer has a melting point of 42° C. to 90° C. as measured with a differential scanning calorimeter.
US09570640B2
A method of manufacturing a solar cell module includes preparing a solar cell substrate including a support substrate, an electric power generating layer that receives light beams and generates electric power, and a conductive layer that is formed on the electric power generating layer, forming a resist layer on the conductive layer in such a manner that an exposed portion at which the conductive layer is exposed is formed, forming an electric conduction portion at a part of the exposed portion, and etching the conductive layer by using the resist layer and the electric conduction portion as a mask.
US09570631B2
A Schottky barrier diode element includes an n-type or p-type silicon (Si) substrate, an oxide semiconductor layer, and a Schottky electrode layer, the oxide semiconductor layer including either or both of a polycrystalline oxide that includes gallium (Ga) as the main component and an amorphous oxide that includes gallium (Ga) as the main component.
US09570627B2
A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, an insulating layer, and a gate electrode. The drain electrode is spaced from the drain electrode. The semiconducting layer is electrically connected to the drain electrode and the source electrode. The semiconducting layer is an oxide semiconductor film comprising indium (In), cerium (Ce), zinc (Zn) and oxygen (O) elements, and a molar ratio of In, Ce, and Zn as In:Ce:Zn is in a range of 2:(0.5 to 2):1. The gate electrode is insulated from the semiconducting layer, the source electrode, and the drain electrode by the insulating layer.
US09570622B2
To provide a highly reliable semiconductor device using an oxide semiconductor. The semiconductor device includes a first electrode layer; a second electrode layer positioned over the first electrode layer and including a stacked-layer structure of a first conductive layer and a second conductive layer; and an oxide semiconductor film and an insulating film positioned between the first electrode layer and the second electrode layer in a thickness direction. The first conductive layer and the insulating film have a first opening portion in a region overlapping with the first electrode layer. The oxide semiconductor film has a second opening portion in a region overlapping with the first opening portion. The second conductive layer is in contact with the first electrode layer exposed in the first opening portion and the second opening portion.
US09570621B2
The present invention discloses a thin film transistor (TFT), a method for manufacturing the TFT, and a display substrate using the TFT that may prevent degradation of the characteristics of an oxide semiconductor contained in the TFT by blocking external light from entering a channel region of the oxide semiconductor. The TFT includes an oxide semiconductor layer; a protective layer overlapping a channel region of the oxide semiconductor layer; an opaque layer disposed between the oxide semiconductor layer and the protective layer; a source electrode contacting a first side of the oxide semiconductor layer; a drain electrode contacting a second side of the oxide semiconductor layer and facing the source electrode across the channel region; a gate electrode to apply an electric field to the oxide semiconductor layer; and a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer.
US09570607B2
In a field-effect semiconductor device, alternating first n-type and p-type pillar regions are arranged in the active area. The first n-type pillar regions are in Ohmic contact with the drain metallization. The first p-type pillar regions are in Ohmic contact with the source metallization. An integrated dopant concentration of the first n-type pillar regions substantially matches that of the first p-type pillar regions. A second p-type pillar region is in Ohmic contact with the source metallization, arranged in the peripheral area and has an integrated dopant concentration smaller than that of the first p-type pillar regions divided by a number of the first p-type pillar regions. A second n-type pillar region is arranged between the second p-type pillar region and the first p-type pillar regions, and has an integrated dopant concentration smaller than that of the first n-type pillar regions divided by a number of the first n-type pillar regions.
US09570601B2
Provided is a technique of securing reliability of a gate insulating film, as much as in a Si power MOSFET, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an SiC power MOSFET. In order to achieve this object, in the in the SiC power MOSFET, the gate electrode GE is formed in contact with the gate insulating film GOX, and is formed of the polycrystalline silicon film PF1 having the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film PF2 formed in contact with the polycrystalline silicon film PF1, and having any thickness.
US09570575B1
Aspects include a semiconductor structure and fabrication method. A semiconductor structure may include alternating first and second crystalline layers and a capacitor. The capacitor may include a first terminal, a second terminal, and a dielectric. The first terminal may include a first central portion and first lobes extending laterally from the first central portion. The second terminal may include a second central portion and second lobes extending laterally from the second central portion. A portion of the second lobes may be fitted between consecutive first lobes. The fabrication method may include forming alternating first and second crystalline layers, forming a first trench, selectively etching the first crystalline layers within the first trench, depositing a dielectric in the first trench, filling the first trench with a metal, forming a second trench, etching the first and second crystalline layers within the second trench, and filling the second trench with a metal.
US09570573B1
A method for forming a gate tie-down includes exposing an active area to form trench contact openings and forming trench contacts therein. An etch stop layer is formed on the trench contacts and on spacers of adjacent gate structures. An interlevel dielectric (ILD) is deposited to fill over the etch stop layer. The ILD and the etch stop layer on one side of the gate structure are opened up to provide an exposed etch stop layer portion. The gate structure is recessed to expose a gate conductor. The exposed etch stop layer portion is removed. A conductive material is deposited to provide a self-aligned contact down to the trench contact on the one side of the gate structure, to form a gate contact down to the gate conductor and to form a horizontal connection within the ILD over the active area between the gate conductor and the self-aligned contact.
US09570572B2
There is set forth herein a method of fabricating a contact interface formation. A layer of Ti metal can be deposited on a substrate and a layer of Ni metal can be deposited over the layer of Ti metal. An annealing process can be performed to form a contact interface formation having Ti in reacted form and Ni in reacted form.
US09570569B2
A complementary metal-oxide semiconductor (CMOS) device and a method of fabricating a CMOS device are described. The method includes forming an interfacial layer in a trench on a substrate in both a p-channel field effect transistor (pFET) area of the CMOS device and an n-channel FET (nFET) area of the CMOS device, depositing a high-k dielectric on the interfacial layer in both the pFET area and the nFET area, selectively forming a first metal layer on the high-k dielectric in only the pFET area, and depositing a second metal layer on the first metal layer in the pFET area and on the high-k dielectric in the nFET area. The method also includes performing an anneal that increases a thickness of the interfacial layer in only the pFET area.
US09570558B2
An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.
US09570556B1
A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure. The first fin structure and the second fin structure are both disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction in plan view. A first void is formed in the source/drain structure, and a second void is formed in the source/drain structure and located above the first void.
US09570554B2
After formation of a gate structure and a lower dielectric spacer laterally surrounding the gate structure, a disposable material layer is deposited and planarized such that the top surface of the disposable material layer is formed below the topmost surface of the lower dielectric spacer. An upper dielectric spacer is formed around the gate structure and over the top surface of the disposable material layer. The disposable material layer is removed selective to the upper and lower dielectric spacers and device components underlying the gate structure. Semiconductor surfaces of the gate structure can be laterally sealed by the stack of the lower and upper dielectric spacers. Formation of any undesirable semiconductor deposition on the gate structure can be avoided by the combination of the lower and upper dielectric spacers during a subsequent selective epitaxy process.
US09570552B1
A method of forming symmetrical stress liners to maintain strain in CMOS vertical NW FETs and the resulting device are provided. Embodiments include providing a doped semiconductor layer on an upper surface of a substrate; providing a semiconductor nanowire on the doped semiconductor layer; forming a first stress layer on the doped semiconductor layer surrounding the semiconductor nanowire; forming a gate electrode layer on a portion of the first stress layer on opposite sides of the semiconductor nanowire; forming a gate dielectric layer on the first stress layer between the gate electrode layer and the semiconductor nanowire; forming an oxide layer on a remaining portion of the first stress layer; forming a second stress layer on the oxide layer, the gate dielectric layer and the gate electrode layer; and forming contacts to the gate electrode layer, the semiconductor nanowire, and the doped semiconductor layer.
US09570549B2
A semiconductor nanocrystal and a preparation method thereof, where the semiconductor nanocrystal include a bare semiconductor nanocrystal and a water molecule directly bound to the bare semiconductor nanocrystal.
US09570548B2
Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.
US09570541B2
A semiconductor device is disclosed. In a surface layer of a front surface of an n-type semiconductor substrate, an anode layer is provided in an element activation portion and an annular p-type guard ring and an n-type high-concentration surface region are provided in an annular termination breakdown voltage region which surrounds the outer circumference of the anode layer. The impurity concentration of the n-type high-concentration surface region is higher than that of the semiconductor substrate and is lower than that of the p-type guard ring. The depth of the n-type high-concentration surface region is less than that of the guard ring. The anode layer and the guard ring are formed while the oxygen concentration of the semiconductor substrate is set to be equal to or more than 1×1016/cm3 and equal to or less than 1×1018/cm3.
US09570535B2
The present invention relates to an integrated magnetics component comprising a magnetically permeable core comprising a base member extending in a horizontal plane and first, second, third and fourth legs protruding substantially perpendicularly from the base member. First, second, third and fourth output inductor windings are wound around the first, second, third and fourth legs, respectively. A first input conductor of the integrated magnetics component has a first conductor axis and extends in-between the first, second, third and fourth legs to induce a first magnetic flux through a first flux path of the magnetically permeable core. A second input conductor of the integrated magnetics component has a second coil axis extending substantially perpendicularly to the first conductor axis to induce a second magnetic flux through a second flux path of the magnetically permeable core extending substantially orthogonally to the first flux path. Another aspect of the invention relates to a multiple-input isolated power converter comprising the integrated magnetics component.
US09570531B2
An organic light emitting display device includes a substrate comprising a major surface; a display region and a peripheral region surrounding the display region when viewed in a viewing direction perpendicular to the major surface; an array of a plurality of pixels disposed in the display region; and a first power line extending from the peripheral region into the display region, the first power line being electrically connected to the array of pixels at a contact point in the display region. When viewed in the viewing direction, the first power line includes: a first extension extending from the peripheral region to the display region; and a second extension connected to the first extension; and a third extension connected to the second extension and extending from a location in the display region toward the peripheral region.
US09570529B2
An organic light emitting diode (OLED) display including a display substrate; a sealing member facing the display substrate; a sealant between the display substrate and the sealing member, the sealant cohering the display substrate and the sealing member; a plurality of conductive wires on the display substrate and overlapping the sealant; and a heat blocking film between the conductive wire and the sealant, the heat blocking film including a plurality of sub-heat blocking films.
US09570527B2
An organic light emitting diode display may include a front display part including a plurality of front pixels formed on a substrate and realizing an image at a front and a side display part. A side pixel of the side display part may include: a plurality of thin film transistors formed on the substrate; a protective layer covering the plurality of thin film transistor and having an inclination groove that is oblique; a first electrode formed at the inclination groove of the protective layer; a pixel defining layer having an opening exposing the first electrode and formed on the protective layer; an organic emission layer formed on the first electrode and the pixel defining layer; and a second electrode covering the organic emission layer.
US09570526B2
An organic light emitting display device and a method for manufacturing the organic light emitting display device, which includes a light emitting region and a non-light emitting region, and having an organic light emitting element including first and second electrodes disposed in the light emitting region and an organic emission layer formed between the two electrodes, a driving voltage supply line disposed in the non-light emitting region and providing a driving voltage to the first and second electrodes, and a contact part disposed in the non-light emitting region and disposed to be in contact with the first electrode to supply the driving voltage provided from the driving voltage supply line to the first electrode, wherein the contact part is formed as multiple layers patterned such that a second conductive layer covers a first conductive layer.
US09570524B2
Provided is a flexible organic light emitting diode display panel including: a substrate in which an opening region and a non-opening region are defined; an organic light emitting diode disposed on the substrate; a bank layer disposed in the non-opening region; and a peeling reduction layer having a reverse-tapered shape disposed in the non-opening region.
US09570518B2
A light emitting element is provided, including a first electrode layer, a second electrode layer, and an organic light emitting layer sandwiched between the first electrode layer and the second electrode layer. The organic light emitting layer is patterned to include a plurality of light emitting blocks with different densities. In an embodiment, the light emitting blocks are divided into a plurality of light emitting block groups that are arranged in an alternate manner. In another embodiment, a light emitting element includes a first electrode layer, a first organic light emitting layer, a charge generating layer, a second organic light emitting layer, and a second electrode layer sequentially stacked on one another. The first and second organic light emitting layer are patterned to form a plurality of first and second light emitting blocks with different densities, respectively. Thus, the light emitting element generates full-color, gray-scale, three-dimensional, or dynamic images.
US09570517B2
An organic light emitting display device includes a substrate and a plurality of pixels defined in the substrate. A pixel includes red subpixel, green subpixel, blue subpixel, and white subpixel. The organic light emitting display device includes an anode electrode formed on the substrate, a cathode electrode opposing the anode electrode, and a red common emission layer, a green common emission layer, and a blue common emission layer formed across each of the red, green, blue and white subpixel areas. The blue common emission layer is disposed above and adjacent to the anode electrode, the green common emission layer is disposed above the blue common emission layer, and the red common emission layer is disposed above the green common emission layer and adjacent to the cathode electrode.
US09570515B2
A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
US09570514B2
According to an embodiment, a semiconductor device includes two electrodes extending in a first direction, a semiconductor layer provided between the two electrodes, an insulating film disposed between the two electrodes. The two electrodes are arranged in a second direction intersecting the first direction. The semiconductor layer extends in a third direction orthogonal to the first direction and the second direction. The insulating film covers a side surface of the semiconductor layer opposite to one of the two electrodes. The semiconductor layer has a shape in a cross section perpendicular to the third direction such that a width in the first direction at a center of the cross section is narrower than a width, in the first direction, of the side surface.
US09570512B2
A resistive random access memory (RRAM) structure is formed on a supporting substrate and includes a first electrode and a second electrode. The first electrode is made of a silicided fin on the supporting substrate and a first metal liner layer covering the silicided fin. A layer of dielectric material having a configurable resistive property covers at least a portion of the first metal liner. The second electrode is made of a second metal liner layer covering the layer of dielectric material and a metal fill in contact with the second metal liner layer. A non-volatile memory cell includes the RRAM structure electrically connected between an access transistor and a bit line.
US09570504B2
Provided is a method of manufacturing an imaging apparatus. The imaging apparatus is formed on a substrate and includes a pixel region and a peripheral circuit region that is arranged on a periphery of the pixel region. The method includes: forming an insulating layer in the pixel region and the peripheral circuit region; etching the insulating layer formed in the pixel region in a state in which the peripheral circuit region is protected; planarizing a surface of the insulating layer; and forming a waveguide in the pixel region. After the forming an insulating layer and before the etching the insulating layer, an average value of heights of a top surface of the insulating layer in the pixel region is larger than an average value of heights of a top surface of the insulating layer in the peripheral circuit region.
US09570481B2
A display substrate includes a first switching element, an organic layer disposed on the first switching element, a capping layer disposed on the organic layer and a cover electrode covering the first emission hole. The first switching element is electrically connected to a gate line extending in a first direction, a data line extending in a second direction crossing the first direction and the pixel electrode disposed adjacent to the data line. The capping layer includes a first emission hole. The cover electrode overlaps the gate line as a first width. The cover electrode overlaps the first switching element as a second width. The second width is smaller than the first width.
US09570474B2
A display device includes a substrate including a plurality of pixel areas, a thin film transistor disposed on the substrate, a color filter and a light blocking member disposed on the thin film transistor, an insulating layer which is disposed on the color filter and the light blocking member and includes an exposed region through which the light blocking member is exposed, a pixel electrode which is disposed on the insulating layer and is connected to the thin film transistor through a contact hole, a common electrode which is spaced apart from the pixel electrode with a microcavity therebetween, a roof layer disposed on the common electrode, a liquid crystal layer which is filled in the microcavity, and an overcoat which is disposed on the roof layer and configured to seal the microcavity.
US09570462B2
A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.
US09570457B2
A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. A semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.
US09570454B2
The present disclosure relates to an integrated chip having a FinFET device and an embedded flash memory device, and a method of formation. In some embodiments, the integrated chip has a logic region and a memory region that is laterally separated from the logic region. The logic region has a first plurality of fins of semiconductor material protruding outward from a semiconductor substrate. A gate electrode is arranged over the first plurality of fins of semiconductor material. The memory region has a second plurality of fins of semiconductor material extending outward from the semiconductor substrate. An embedded flash memory cell is arranged onto the second plurality of fins of semiconductor material. The resulting integrated chip structure provides for good performance since it contains both a FinFET device and an embedded flash memory device.
US09570452B2
A flash memory fabrication method includes: providing a substrate having a plurality of floating gate structures separated by trenches, which includes at least a source trench and a drain trench, and source/drain regions; forming a metal film on the substrate and on the floating gate structures; performing a thermal annealing process on the metal film to form a first silicide layer on the source regions and a second silicide layer on the drain regions; removing portions of the metal film to form a metal layer on the bottom and lower sidewalls of the source trench and contacting with the first silicide layer, and forming a dielectric layer on the substrate and the floating gate structures, covering the source trench and the drain trench. Further, the method includes forming a first conducting structure and one or more second conducting structures in the dielectric layer. The first conducting structure is on the metal layer in the source trench, the second conducting structures are on the second silicide layer, and adjacent first conducting structure and second conducting structure have a predetermined distance.
US09570451B1
A method of forming semiconductor devices. First, a substrate is provided, and a first implant area and a second implant area are defined in a mask pattern. Subsequently, a resist layer on the substrate is patterned using the mask pattern to form a first opening exposing the first implant area and a second opening to expose the second implant area. After that, an ion implantation process including a partial shadowing ion implant is processed, wherein the second implant area is implanted by the partial shadowing ion implant to a predetermined concentration, and the first implant area is substantially not implanted by the partial shadowing ion implant.
US09570447B2
One semiconductor device includes first to third gate electrodes arranged inside a first active region and embedded in first to third trenches extending in a first direction, a first semiconductor pillar positioned between the first and second trenches, a second semiconductor pillar positioned between the second and third trenches, a first vertical transistor having the first and second gate electrodes as the double gate electrodes therefor, and a second vertical transistor having the second and third gate electrodes as the double gate electrodes therefor. The second gate electrode is shared by the first vertical transistor and the second vertical transistor.
US09570445B2
A semiconductor device having a novel structure is provided. The semiconductor device includes a first p-type transistor, a second n-type transistor, a third transistor, and a fourth transistor. One of a source and a drain of the third transistor is connected to a wiring supplying first potential, and the other is connected to one of a source and a drain of the first transistor. One of a source and a drain of the second transistor is connected to the other of the source and the drain of the first transistor, and the other is connected to one of a source and a drain of the fourth transistor. The other of the source and the drain of the fourth transistor is connected to a wiring supplying second potential lower than the first potential. An oxide semiconductor material is used in channel formation regions of the third transistor and the fourth transistor.
US09570442B1
Aspects for applying channel stress to Fin field-effect transistors (FETs) (FinFETs) using a self-aligned single diffusion break (SDB) isolation structure are disclosed. In one aspect, a FinFET-based circuit is provided. The FinFET-based circuit includes a semiconductor substrate and a Fin formed from the semiconductor substrate. The FinFET-based circuit also includes first and second FinFETs, each corresponding to the Fin. The FinFET-based circuit also includes a gate region disposed between the first FinFET and the second FinFET. An SDB isolation structure is formed in the Fin between the first FinFET and the second FinFET. The self-aligned SDB isolation structure is self-aligned with the gate region and electrically isolates the first FinFET and the second FinFET. The self-aligned SDB isolation structure applies stress to a first channel corresponding to the first FinFET and to a second channel corresponding to the second FinFET.
US09570436B2
The present invention provides a semiconductor device that prevents destruction due to an avalanche breakdown and that has a high tolerance against breakdown by configuring the device so as to have a punch-through breakdown function therein and such that the breakdown voltage of a punch-through breakdown is lower than an avalanche breakdown voltage so that an avalanche breakdown does not occur.
US09570435B2
A semiconductor element is provided which does not break down by avalanche current. A surge protection element includes: a semiconductor multi-layer comprising a nitride semiconductor; a first p-type semiconductor and a second p-type semiconductor which are disposed above the semiconductor multi-layer; a first electrode disposed above the first p-type semiconductor; and a second electrode disposed above the second p-type semiconductor.
US09570433B2
A semiconductor device includes a semiconductor substrate including a main surface with a polygonal geometry and a main electric circuit manufactured within a main region on the semiconductor substrate. The main electric circuit is operable to perform an electric main function. The main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate. The corner area extends at least 300 μm along the edges of the semiconductor substrate beginning at the corner.
US09570420B2
Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.
US09570417B2
The chip bonding apparatus used in a chip bonding method includes a heating unit for heating an anisotropic conductive film at a first temperature; an attachment unit for attaching an integrated circuit chip to the anisotropic conductive film; a stage on which a substrate is seated; a chip transport unit for moving and aligning the integrated circuit chip that is attached to the anisotropic conductive film on the substrate; and a bonding head arranged above the stage to bond the integrated circuit chip that is attached to the anisotropic conductive film onto the substrate through thermo-compression of the integrated circuit chip onto the substrate at a second temperature that is lower than the first temperature.
US09570407B2
A method for manufacturing a semiconductor device includes: a fixing step in which semiconductor chips are mounted on and fixed to predetermined positions on an upper surface of a single starting substrate to form individual substrates; a connection step in which electrodes of the semiconductor chips and of the starting substrate are connected by wires; a sealing step in which on the upper surface of the starting substrate, the resin is potted among the semiconductor chips to seal an entire lateral circumference of each of the semiconductor chip; a bonding step in which a single starting protective cover to form individual protective covers is bonded to a surface of the resin so as to extend the semiconductor chips; and a cutting step in which an assembly of the semiconductor devices formed by bonding the starting protective cover to the starting substrate via the resin is cut to the semiconductor devices.
US09570399B2
The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor die mounted on a base. The first semiconductor die includes a semiconductor substrate. A first array of TSV interconnects and a second array of TSV interconnects are formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. A first ground TSV interconnect is disposed within the interval region. A second semiconductor die is mounted on the first semiconductor die, having a ground pad thereon. The first ground TSV interconnect of the first semiconductor die has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.
US09570392B2
According to one embodiment, a memory device includes a conductive member and a stacked body provided on the conductive member. The stacked body includes a plurality of first interconnections being stacked to be separated from each other, a memory cell connected with one of the first interconnections, a plurality of contact plugs, an insulating member. Each of the contact plugs connects each of the first interconnections with an upper surface of the conductive member. One of the contact plugs includes an upper part, and a lower part. The lower part is provided between the upper part and the conductive member. The lower part includes a first portion and a second portion. The first portion is connected with one of the first interconnections. The second portion is connected with the conductive member. The insulating member is provided between the first portion and the second portion.
US09570386B2
A flexible interposer for the attachment of a microelectronic package to a microelectronic socket, wherein a first portion of the flexible substrate may be positioned between the microelectronic package and the microelectronic socket, and a second portion of the flexible interposer may extend from between the microelectronic package and the microelectronic socket to electrically contact an external component. In one embodiment, the external component may be a microelectronic substrate and the microelectronic socket may be attached to the microelectronic substrate.
US09570384B2
A semiconductor device can include a substrate and a trace layer positioned in proximity to the substrate and including a trace for supplying an electrical connection to the semiconductor device. Conductive layers can be positioned in proximity to the trace layer and form a bond pad. A non-conductive thin film layer can be positioned between the trace layer and the conductive layers. The thin film layer can include a via to enable the electrical connection from the trace to the bond pad. A portion of the trace between the substrate and the plurality of conductive layers can have a beveled edge.
US09570382B2
A microelectronic package has a microelectronic element overlying or mounted to a first surface of a substrate and substantially rigid conductive posts projecting above the first surface or projecting above a second surface of the substrate remote therefrom. Conductive elements exposed at a surface of the substrate opposite the surface above which the conductive posts project are electrically interconnected with the microelectronic element. An encapsulant overlies at least a portion of the microelectronic element and the surface of the substrate above which the conductive posts project, the encapsulant having a recess or a plurality of openings each permitting at least one electrical connection to be made to at least one conductive post. At least some conductive posts are electrically insulated from one another and adapted to simultaneously carry different electric potentials. In particular embodiments, the openings in the encapsulant at least partially expose conductive masses joined to posts, fully expose top surfaces of posts and partially expose edge surfaces of posts, or may only partially expose top surfaces of posts.
US09570376B2
A chip package includes a first substrate having at least one circuit layer formed on a first surface thereof, a first die mounted on a second surface of the first substrate opposite from the first surface, and an interconnection assembly comprising upper and lower conductive layers provided on an insulating substrate, with the upper conductive layer of the interconnection assembly affixed to the second surface of the first substrate and electrically connected to the at least one circuit layer of the first substrate. A second substrate is positioned on a side of the first die opposite from the first substrate so as to position the die between the first and second substrates, the second substrate having at least one circuit layer formed on an outward facing first surface thereof that is electrically connected to at least one of the lower conductive layers of the interconnection assembly and the first die.
US09570372B1
The present invention relates to methods of making a semiconductor assembly having a semiconductor device embedded in a heat spreader and electrically connected to a dual-stage formed interconnect substrate. In a preferred embodiment, the interconnect substrate consists of first and second build-up circuitries and the methods are characterized by the step of attaching a semiconductor subassembly having a first build-up circuitry adhered to a sacrificial carrier to a heat spreader using an adhesive with the semiconductor device inserted into a cavity of the heat spreader and the step of detaching the sacrificial carrier from the first build-up circuitry. The heat spreader provides thermal dissipation, and the first and second build-up circuitries provide staged fan-out routing for the semiconductor device.
US09570369B1
A semiconductor package includes a redistributed layer (RDL) interposer having a first side, a second side opposite to the first side, and a vertical sidewall extending between the first side and the second side; at least one semiconductor die mounted on the first side of the RDL interposer; a molding compound disposed on the first side and covering the at least one semiconductor die and the vertical sidewall of the RDL interposer; and a plurality of solder bumps or solder balls mounted on the second side.
US09570368B2
A method of forming a semiconductor package includes forming a passivation layer over a semiconductor substrate. The semiconductor substrate includes a first chip region, a second chip region and a scribe line region. The scribe line region is positioned between the first chip region and the second chip region. The method also includes forming a bump over the passivation layer on at least one of the first chip region and the second chip region. The method further includes removing a portion of the passivation layer to form a groove in the passivation layer on the scribe line region. The method additionally includes filling the groove with a molding compound layer. The molding compound layer is filled to a point that entirely fills the groove, covers the passivation layer, and covers a lower portion of the bump. The method also includes separating the first chip region from the second chip region along the scribe line region.
US09570365B2
The present disclosure provides a display device, including: a display region; and a non-display region adjacent to the display region, wherein the non-display region includes: a gate-driving circuit; a driving unit; and a test pad, wherein the driving unit electrically connects the gate-driving circuit through the test pad. The present disclosure also provides a test pad.
US09570363B2
A method of forming a vertically integrated memory cell including a deep trench extending into a substrate, a trench capacitor located within the deep trench, and a vertical transistor at least partially embedded within the deep trench above the trench capacitor, the vertical transistor is in direct contact with and electrically coupled to the trench capacitor.
US09570362B2
A method for manufacturing a semiconductor device including a MOS transistor comprising forming a gate electrode on a first insulating film formed on a substrate, performing ion implantation into the substrate and forming a diffusion region, and forming a second insulating film on the substrate, in that order. The performing ion implantation comprises forming a first resist pattern, performing the ion implantation using the first resist pattern as a mask and removing the first resist pattern, including removing, by asking, a part of the first resist pattern hardened by the ion implantation and then removing the remaining part. In forming the gate electrode, a gate electrode material layer is patterned and a protective film is formed.
US09570360B2
Silicon fins are formed in a bulk silicon substrate and thereafter trench isolation regions are formed between each silicon fin. The silicon fins in nFET and pFET device regions are then recessed. A relaxed silicon germanium alloy fin portion is formed on a topmost surface of each recessed silicon fin portion or on exposed surface of the substrate. A compressively strained silicon germanium alloy fin portion is formed on each relaxed silicon germanium alloy fin portion within the pFET device region, and a strained silicon-containing fin portion is formed on each relaxed silicon germanium alloy fin portion within the nFET device region. Sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion are then exposed. A functional gate structure is provided on the exposed sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion.
US09570354B2
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
US09570344B2
A method can include forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the forming including using a hardmask layer, and filling the contact trench with a sacrificial material layer, the sacrificial material layer formed over the contact formation. A semiconductor structure can include a sacrificial material layer over a contact formation.
US09570336B2
A substrate transfer system includes a substrate transfer robot. The substrate transfer robot is provided between a first apparatus and a second apparatus which has a wall provided opposite to the substrate transfer robot and having an opening on the wall. The substrate transfer robot is configured to transfer a substrate from the first apparatus to the second apparatus via the opening and includes a base having a first axis, an arm body, and a hand. The arm body has a proximal end and a distal end and is connected to the base at the proximal end to rotate around the first axis. The substrate transfer robot includes a minimum distance from the first axis to an outermost portion of the arm body and the hand in a radius direction from the first axis being larger than a distance between the first axis and the opening on the wall.
US09570331B2
A wafer cassette includes a main body having space to hold at least one wafer assembly. Each of the at least one wafer assembly includes a wafer and an electrostatic carrier attached to the wafer. An electrical contact structure inside the main body is arranged to contact an electrical pad of the electrostatic carrier.
US09570328B2
Apparatus for use with multi-zonal heating sources are provided. In some embodiments, a substrate support may have a pocket disposed in a surface of the substrate support and a lip disposed about the pocket to receive an edge of a substrate and to support the substrate over the pocket such that a gap is defined between a pocket surface and a backside surface of the substrate when the substrate is disposed on the lip; a plurality of features to operate in combination with a plurality of heating zones provided by a multi-zonal heating source to provide a desired temperature profile on a frontside surface of a substrate when the substrate is disposed on the lip, and wherein the plurality of features are alternatingly disposed above and below a baseline surface profile of the pocket surface in a radial direction from a central axis of the substrate support.
US09570326B2
A substrate cleaning method includes: a first step in which a cleaning liquid is ejected from a nozzle N2 to a central portion of a wafer W; a second step in which a dry gas is ejected from a nozzle N3 to the central portion of the wafer W to form a dry area; a third step in which the cleaning liquid is ejected from the nozzle N2 while the nozzle N2 is moved from a central side of the wafer W to a peripheral side thereof; a fourth step in which a width of an intermediate area generated between a wet area and the dry area is acquired; and a fifth step in which, when the width of the intermediate area exceeds a predetermined threshold value, a process parameter is changed such that the width of the intermediate area becomes the threshold value or less.
US09570325B2
A packaged semiconductor device, such as a power QFN device, has (rectangular) ribbon wires, instead of circular bond wires. A proximal end of each ribbon wire is connected to a pad on an IC die, and a distal end of each ribbon wire forms a device lead. The die and the ribbon wires are encapsulated in a molding compound with a side of each device lead exposed. Such devices can be assembled without using lead frames. The omission of lead frames and the use of ribbon wires enable assembly of smaller devices having enhanced thermal dissipation capabilities.
US09570322B2
Packages and methods of manufacture thereof are described. A package may include a first package and a die structure disposed over the first package. The first package may include: a first encapsulant; a first via structure within the first encapsulant; a first die within the first encapsulant, at least a portion of the first encapsulant being interposed between a sidewall of the first die and a sidewall of the first via structure; a second die within the first encapsulant, an active side of the second die facing an active side of the first die; and a first via chip within the first encapsulant, the first via chip comprising one or more through vias, wherein the first via chip is disposed at the active side of the first die, and between the second die and the first via structure.
US09570308B2
A method for fabricating a semiconductor device includes: implanting a first species into a substrate at a cold temperature to form a first region; and implanting a second species into the substrate at a hot temperature to form a second region that is adjacent to the first region.
US09570305B2
A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer and masking layers over the dielectric layer. A thin spacer layer is used to form spacers alongside a pattern. A reverse image of the spacer pattern is formed and an enlargement process is used to slightly widen the pattern. The widened pattern is subsequently used to pattern an underlying layer. This process may be used to form a pattern in a dielectric layer, which openings may then be filled with a conductive material.
US09570304B2
Provided is a method of fabricating a semiconductor device. The method includes forming an anti-reflection layer on a lower layer, forming photoresist patterns on the anti-reflection layer, forming protection patterns to cover the photoresist patterns, respectively, etching the anti-reflection layer using the photoresist patterns covered with the protection patterns as an etch mask to form anti-reflection patterns, forming spacers to cover sidewalls of the anti-reflection patterns, and removing the anti-reflection patterns.
US09570297B1
A method of forming a semiconductor in a long trench. The method may include; forming a first semiconductor on a substrate and in a long trench; forming a first spacer along sidewalls of the long trench and above the first semiconductor, a portion of the first semiconductor remains exposed; recessing the exposed portion of the first semiconductor; forming an insulator layer on the recessed portion of the first semiconductor; forming a second semiconductor on the insulator layer; forming a second spacer on sidewalls of the first spacer and above the second semiconductor, a portion of the second semiconductor remains exposed; removing the exposed portion of the second semiconductor; and removing a frond end and a back end of the first semiconductor and the second semiconductor, wherein the front end and back end are separated by a central region and the central region extends across the width of the long trench.
US09570289B2
A method of minimizing a seam effect of a deposited TEOS oxide film during a trench filling process performed on a semiconductor substrate in a semiconductor substrate plasma processing apparatus comprises supporting a semiconductor substrate on a pedestal in a vacuum chamber thereof. Process gas including TEOS, an oxidant, and argon is flowed through a face plate of a showerhead assembly into a processing region of the vacuum chamber. RF energy energizes the process gas into a plasma wherein TEOS oxide film is deposited on the semiconductor substrate so as to fill at least one trench thereof. The argon is supplied in an amount sufficient to increase the electron density of the plasma such that the deposition rate of the TEOS oxide film towards the center of the semiconductor substrate is increased and the seam effect of the deposited TEOS oxide film in the at least one trench is reduced.
US09570275B2
The present disclosure generally comprises a heated showerhead assembly that may be used to supply processing gases into a processing chamber. The processing chamber may be an etching chamber. When processing gas is evacuated from the processing chamber, the uniform processing of the substrate may be difficult. As the processing gas is pulled away from the substrate and towards the vacuum pump, the plasma, in the case of etching, may not be uniform across the substrate. Uneven plasma may lead to uneven etching. To prevent uneven etching, the showerhead assembly may be separated into two zones each having independently controllable gas introduction and temperature control. The first zone corresponds to the perimeter of the substrate while the second zone corresponds to the center of the substrate. By independently controlling the temperature and the gas flow through the showerhead zones, etching uniformity of the substrate may be increased.
US09570269B2
A method for manufacturing a TEM-lamella is disclosed. The method includes: disposing a self-supporting protective structure on a surface of a substrate; bonding the protective structure to the substrate; cutting out a lamella from the substrate using a particle beam so that the lamella remains bonded to at least a portion of the protective structure; fastening a first tool to the lamella; and moving away the lamella from a residual portion of the substrate by moving the first tool relative to the substrate.
US09570268B2
The purpose of the present invention is to provide a charged particle gun using merely an electrostatic lens, said charged particle gun being relatively small and having less aberration, and to provide a field emission-type charged particle gun having high luminance even with a high current. This charged particle gun has: a charged particle source; an acceleration electrode that accelerates charged particles emitted from the charged particle source; a control electrode, which is disposed further toward the charged particle source side than the acceleration electrode, and which has a larger aperture diameter than the aperture diameter of the acceleration electrode; and a control unit that controls, on the basis of a potential applied to the acceleration electrode, a potential to be applied to the control electrode.
US09570267B2
A multi charged particle beam writing method includes performing ON/OFF switching of a beam by an individual blanking system for the beam concerned, for each beam in multi-beams of charged particle beam, with respect to each time irradiation of irradiation of a plurality of times, by using a plurality of individual blanking systems that respectively perform beam ON/OFF control of a corresponding beam in the multi-beams, and performing blanking control, in addition to the performing ON/OFF switching of the beam for the each beam by the individual blanking system, with respect to the each time irradiation of the irradiation of the plurality of times, so that the beam is in an ON state during an irradiation time corresponding to irradiation concerned, by using a common blanking system that collectively performs beam ON/OFF control for a whole of the multi-beams.
US09570262B1
A circuit breaker having a positive-off stop feature includes an operating lever rotatably coupled to a side frame, a tension lever coupled to the side frame, and an upper toggle linkage and a stop link each rotatably coupled to the tension lever. The upper toggle linkage may be configured to rotate the stop link. The operating lever may be configured to move rotatably to and from an ON position and an OFF position provided the main contacts of the circuit breaker are not welded or otherwise stuck together. Should the main contacts become welded or otherwise stuck together, the upper toggle linkage may be configured to rotate the stop link to a position wherein the stop link may be configured to prevent the operating lever from moving into the OFF position. Methods of assembling a circuit breaker positive-off stop feature are also provided, as are other aspects.
US09570259B2
An electromagnetic relay includes: a pair of fixed contact terminals, each of which has a fixed contact; a movable contact spring having a pair of movable pieces and a coupler coupling the pair of movable pieces, each of the movable pieces having a movable contact that contacts and is separated from the fixed contact; an armature having a flat plate to be adsorbed to an iron core and a hanging portion bent from the flat plate and extending downward, and moves the movable contact spring by a rotation operation; and an electromagnetic device driving the armature, wherein the hanging portion has a projection to fix the movable contact spring on a face thereof facing the electromagnetic device and a pulling portion that extends downward more than the projection and pulls the movable contact spring when a current flows between the fixed contact and the movable contact.
US09570258B2
The present invention relates to a magnetic switch, and more particularly, to a magnetic switch provided with a permanent magnet disposed at an outside of an upper frame and an externally fitted permanent magnet holder to reduce a number of components and facilitate maintenance.
US09570254B2
A portable electronic user device, in the form of an electronic key, having an inherently rigid button for activation by a user. The portable electronic user device further has a flexibly deformable membrane including a first side having at least one support section on which the at least one button is supported via the plunger, and an actuating section, separate from the at least one support section, for receiving and forwarding an actuation of the button to an electrical switch element. There is a rigid frame which bears the membrane on a second side opposite the first side, wherein, in the assembled state, having the membrane in the region of the at least one support section, the frame has at least one breakout, via which the membrane is moveable by the plunger upon activating the at least one button and, in dependence on the size and/or the shape of the breakout, provides a force for resetting the button. As a result of the separation of the generating of the reset force on the support sections movable by the first breakouts and the switch function in the region of the activation section, there is great freedom in the design of the portable electronic user device, wherein reliable triggering of the switch element is always ensured.
US09570250B2
A gas insulated switching device with a gastight housing, with switching elements mounted in the housing, having an optical window on which an external camera can be positioned outside the housing on a support element in such, that the contacts and/or the contact positions of one or more switches can be displayed by this camera on a display screen, and with a switchable light source, which illuminates the area the camera is focused on to display the contact positions of one or more switches, as well as a camera system having the switching device. For easier and more cost effective use of a camera system, considering that direct optical control of specific switch positions are often not desired, the camera may be portable and/or positionable only temporarily, and the support element and the camera itself are provided with complementary elements for temporarily positioning the portable camera to the support.
US09570248B2
The invention relates to a linear selector (1) for power-free preselection of tap contacts for a tapped transformer (100). The linear selector (1) according to the invention is cost-effective, simple and compactly constructed. The functions of a selector and a reverser are thus better connected. The linear selector (1) is constructed from a fine selector (2) and a reversing switch (3). The fine selector (2) and the reversing switch (3) are directly driven via a common gear unit (6).
US09570245B2
Provided are a method for producing an electrode material for a vacuum circuit breaker, whereby withstand voltage, high current interruption performance and capacitor switching performance can be improved; an electrode material for a vacuum circuit breaker; and an electrode for a vacuum circuit breaker. A contact material for an electrode for a vacuum circuit breaker has an integral structure consisting of a central member and a Cu—Cr outer peripheral member, the central member having been produced as described above and comprising 30 to 50 wt % of Cu of a particle diameter of 20 to 150 μm and 50 to 70 wt % of Mo—Cr of a particle diameter of 1 to 5 μm, while the outer peripheral member being formed of a material, which is highly compatible with the central member, shows excellent interruption performance and had high withstand voltage, and being provided outside the central member and fixed thereto.
US09570239B2
An electrode forming film includes: a dielectric film; an electrode head part; a first common electrode connected with the electrode head part; a plurality of first split electrodes spaced apart from the first common electrode in the first direction; a second common electrode spaced apart from the first split electrodes in the first direction; a plurality of second split electrodes spaced apart from the second common electrode in the first direction; a plurality of first fuse parts formed between the first common electrode and the first split electrodes; a plurality of second fuse parts formed between the first split electrodes and the second common electrode; and a plurality of third fuse parts formed between the second common electrode and the second split electrodes.
US09570237B2
There is provided multilayer ceramic capacitor including, a ceramic body including a plurality of dielectric layers laminated therein, an active layer including a plurality of first and second internal electrodes alternately exposed through both end surfaces of the ceramic body, with the dielectric layers interposed therebetween, and having capacitance formed therein, an upper cover layer formed on an upper portion of the active layer, a lower cover layer formed on a lower portion of the active layer and having a thickness greater than that of the upper cover layer, first and second dummy electrode terminals provided in the lower cover layer to be alternately exposed through both end surfaces of the lower cover layer, and first and second external electrodes covering the both end surfaces of the ceramic body.
US09570235B2
A multilayer ceramic capacitor that is highly resistant to insulation degradation under high-temperature load includes an inner ceramic layer that has a composition mainly composed of a perovskite-type compound containing Ba and Ti, at least one of Nb and Ta, contains Mn and Al, and optionally contains Mg and a rare-earth element that is at least one of Y, Gd, Tb, Dy, Ho, and Er, with a content of Ti being 100 parts by mole, and (a) a total of Nb and Ta is from about 0.2 to about 1.5 part by mole, (b) Mg is not more than about 0.2 part by mole including 0 part by mole, (c) Mn is from about 1.0 to about 3.5 parts by mole, (d) Al is from about 1.0 to about 4.0 parts by mole, and (e) the rare-earth element is not more than about 0.05 part by mole including 0 part by mole. Furthermore, an average number of particles per one layer of the inner ceramic layer is not more than 3.
US09570222B2
An inductor component includes a plurality of conductive elements, each formed as an individual patch of conductive material, with the conductive elements arranged in a vertical stack and tightly coupled to one another. Dielectric is disposed between more adjacent conductive elements, the dielectric has a permittivity and is sufficiently thin so as to provide a mutual inductance factor of at least one-half or greater between adjacent ones of the conductive elements. The dielectric is typically thinner than the adjacent conductors.
US09570220B2
In one embodiment, a cryocooler assembly for cooling a heat load is provided. The cryocooler assembly includes a vacuum vessel surrounding the heat load and a cryocooler at least partially inserted into the vacuum vessel, the cryocooler including a coldhead. The assembly further includes an actuator coupled to the cryocooler. The actuator is configured to translate the cryocooler coldhead into thermal engagement with the heat load and to maintain constant pressure of the coldhead against the heat load to facilitate maintaining thermal engagement with the heat load as the heat load shrinks during a cool down process.
US09570207B2
Disclosed are electrical contact materials and a method for preparing the same. The electrical contact material includes (i) one or more kinds of metals selected from the group consisting of silver (Ag), copper (Cu) and gold (Au), and an alloy of nickel (Ni); and (ii) carbon nano tubes (CNTs) coated with Ag nanoparticles, Ag plated CNTs, or Ag nanowires, or (i) one or more kinds of metals selected from the group consisting of Ag, Cu, Ni and Au; (ii) a metal oxide that is cadmium oxide, indium oxide, tin oxide, zinc oxide or mixture thereof; and (iii) CNTs coated with Ag nanoparticles, Ag plated CNTs, or Ag nanowires. Accordingly, it is possible to reduce the content of high-priced Ag and to obtain excellent electrical and mechanical properties.
US09570206B2
A solar cell can include a substrate and a semiconductor region disposed in or above the substrate. The solar cell can also include a conductive contact disposed on the semiconductor region with the conductive contact including a paste, a first metal, and a first conductive portion that includes a conductive alloy formed from the first metal at an interface of the substrate and the semiconductor region.
US09570200B2
A resistive memory device includes a memory cell array that includes a plurality of memory layers stacked in a vertical direction. Each of the plurality of memory layers includes a plurality of memory cells disposed in regions where a plurality of first lines and a plurality of second lines cross each other. A bad region management unit defines as a bad region a first memory layer including a bad cell from among the plurality of memory cells and at least one second memory layer.
US09570186B2
Various embodiments address various difficulties with source side sensing difficulties in various memory architectures, such as 3D vertical gate flash and multilevel cell memory. One such difficulty is that with source side sensing, the signal amplitude is significantly smaller than drain side sensing. Another such difficulty is the noise and reduced sensing margins associated with multilevel cell memory. In some embodiments the bit line is selectively discharged prior to applying the read bias arrangement.
US09570181B2
According to an embodiment, a memory system includes first wiring lines; second wiring lines; third wiring lines; fourth wiring lines; and first and second storages. The first storage includes first memory cells arranged at intersections of the first wiring lines and the second wiring lines. Each of the third wiring lines is connected to any one of the first wiring lines. Each of the fourth wiring lines is pre-associated with a logical address specified by a host apparatus. The second storage includes second memory cells arranged at intersections of the third wiring lines and the fourth wiring lines. A resistance state of each of the second memory cells is set to a first resistance state or a second resistance state where a resistance value is lower than that in the first resistance state, according to a correspondence relationship between the logical address and the first wiring line.
US09570180B2
A semiconductor memory device includes a first memory block having a first memory cell transistor and a first select transistor, a second memory block having a second memory cell transistor and a second select transistor, a first select gate line that is electrically connected to a gate of the first select transistor, and a second select gate line that is electrically connected to a gate of the second select transistor. During writing of data to a memory cell transistor in the first block, a first voltage is applied to the first select gate line during a first time period, a second voltage is applied to the second select gate line during a second time period after the first time period, and a third voltage lower than the first voltage is applied to the first select gate line during a third time period after the second time period.
US09570176B2
An operating method of a nonvolatile memory device includes determining whether a memory block is a selected block, and when the memory block is not the selected block, determining whether the memory block shares a block word line with the selected block. The method further includes applying an unselected block word line voltage to word lines of the memory block when the memory block shares the block word line with the selected block, and floating the word lines of the memory block when the memory block does not share the block word line with the selected block.
US09570174B2
Provided are a coding/decoding method for use in a multi-level memory system. The coding method includes searching for a set of symbols that may generate a forbidden pattern that is set initially from an input data stream, and sticking at least one bit included in the searched set of the symbols that may generate the forbidden pattern so as not to generate the forbidden pattern.
US09570170B2
A memory device includes a memory cell array having multiple memory cells arranged respectively in regions where first signal lines cross second signal lines. The memory device further includes a decoder having multiple line selection switch units connected respectively to the of first signal lines. Each of the multiple line selection switch units applies a bias voltage to a first signal line corresponding to each of the multiple line selection switch units in response selectively to a first switching signal and a second switching signal, voltage levels of which are different from each other in activated states.
US09570167B2
A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.
US09570165B2
A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element, and a two-terminal switching element. The first resistive memory element is electrically coupled to the second resistive memory element and to the switching element at a common node.
US09570163B2
Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb.
US09570153B1
A static random access memory (SRAM) with high efficiency. The SRAM has a first bistable cell, a first bit line, a first complementary bit line, a first word line, and a second word line. The first bistable cell has a first access terminal, a second access terminal, a first access switch and a second access switch. The first access switch is controlled by the first word line to couple the first access terminal to the first bit line. The second access switch is controlled by the second word line to couple the second access terminal to the first complementary bit line.
US09570142B2
Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first memory cells, and a second memory chip having second memory cells. The first memory cells may be refreshed in response to a first clock signal based on the original clock signal. The second memory cells may be refreshed in response to a second clock signal based on the original clock signal.
US09570133B2
A memory circuit with a word line driver and control circuitry is disclosed. The word line driver receives a first voltage reference signal, a second voltage reference signal, and an input signal. The word line driver has an output coupled to a word line. The control circuitry is configured to deselect the word line by applying the input signal to the input of the word line driver. For example, in a program operation the word line is deselected to indicate that the word line is not programmed, and another word line is selected to be programmed. During an operation in which the word line is deselected and another word line is selected, the word line discharges through both of a first p-type transistor and a first n-type transistor of the word line driver.
US09570120B2
A memory device may include a plurality of cell arrays, a first interface suitable for inputting/outputting first data between the plurality of cell arrays and a host apparatus, a second interface suitable for inputting/outputting second data between the plurality of cell arrays and a device other than the host apparatus, and a data erasure circuit suitable for erasing the first data of the plurality of cell arrays when a first mode in which the first interface is used switches to a second mode in which the second interface is used.
US09570118B2
Circuits, architectures, a system and methods for memories with multiple power supplies and/or multiple low power modes. The circuit generally includes peripheral circuitry operating at a first voltage, a memory array operating at a second voltage, and translation circuitry configured to receive an input from the peripheral circuitry at the first voltage and provide an output to the memory array at the second voltage, the translation circuitry further configured to prevent leakage during a standard operating mode of the memory. The method generally includes operating peripheral circuitry at a first voltage from a first power rail, operating a memory array at the first voltage or a second voltage, the memory array being coupled to a second power rail, coupling the first and second power rails during standard operating mode when the memory array operates at the first voltage, otherwise not coupling the first and second power rails, and reducing leakage in the memory array during a leakage reduction mode by reducing a voltage differential between a ground plane in the memory array and the second power rail.
US09570116B2
To provide a small, highly reliable memory device with a large storage capacity. A semiconductor device includes a circuit for retaining data and a circuit for reading data. The circuit for retaining data includes a transistor and a capacitor. The circuit for reading data is configured to supply a potential to the circuit for retaining data and read a potential from the circuit for retaining data. The circuit for retaining data and the circuit for reading data are provided in different layers, so that the semiconductor device with a large storage capacity is manufactured.
US09570110B2
The present invention relates to a multimedia-data-processing method which enables a media graph to always be constructed in a “connection without negotiation” manner, on the basis of an already known media graph construction, and thus provides a media framework in which procedures for connecting components are minimized, thereby improving the performance of a system and satisfying the requests of an OS platform builder and a media application developer. The multimedia-data-processing method of the present invention is performed by a multimedia framework, and comprises: (a) a step of receiving component information required for the construction of the media graph and component connection information from a media application; and (b) a step of ensuring that the media graph is constructed by the content received in step (a), and that the media graph waits for a rendering command, thereby eliminating the necessity of permitting the media application to check the construction of the media graph.
US09570109B2
The present application relates to the field of media processing and more particularly to audio and video processing. The present application addresses the problem that videos collected by fans at concerts and other events generally have poor sound quality and provides a solution that matches a high quality sound to the video.
US09570103B2
Disclosed are a method and apparatus for a data storage library comprising a first and second drive, a first and second mobile medium, a first and second partition wherein the first partition comprises the first drive and the first mobile medium and the second partition comprises the second drive and the second mobile medium, and a combination bridge controller device. The combination bridge controller device is configurable to control first communication traffic between at least a first client and the first partition wherein the first communication traffic can comprise a first data package. The combination bridge controller device is further configurable to optionally encrypt the first data package for storage on the first mobile medium when the first mobile medium is in cooperation with the first drive.
US09570084B2
A processing method for identifying data by an audio conversion device includes: connecting the audio conversion device to a first terminal; sending an identification code stored in the audio conversion device to the first terminal, and sending the identification code to a server via the first terminal, wherein the identification code is used to identify the audio conversion device; obtaining user data; uploading the user data to the server, such that the server stores a correspondence between the identification code and the user data; connecting the audio conversion device to a second terminal; sending the identification code stored in the audio conversion device to the second terminal; sending a data obtaining request containing the identification code to the server; and receiving the user data sent corresponding to the identification code in response to the data obtaining request, or receiving multimedia data matching multimedia using feature information in the user data.
US09570072B2
An exemplary noise reduction system and method processes a speech signal that is delivered in a noisy channel or with ambient noise. Some exemplary embodiments of the system and method use filters to extract speech information, and focus on a subset of harmonics that are least corrupted by noise. Some exemplary embodiments disregard signal harmonics with low signal-to-noise ratio(s), and disregard amplitude modulations that are inconsistent with speech. An exemplary system and method processes a signal that focuses on a subset of harmonics that are least corrupted by noise, disregards the signal harmonics with low signal-to-noise ratio(s), and disregards amplitude modulations that are inconsistent with speech.
US09570065B2
Techniques for performing multi-style speech synthesis. The techniques include using at least one computer hardware processor to perform: obtaining input comprising text and an identification of a first speaking style to use in rendering the text as speech; identifying a plurality of speech segments for use in rendering the text as speech, the identified plurality of speech segments comprising a first speech segment having the first speaking style and a second speech segment having a second speaking style different from the first speaking style; and rendering the text as speech having the first speaking style, at least in part, by using the identified plurality of speech segments.
US09570059B2
A system and methods for acquiring cadence and selecting a song version based on the acquired cadence are disclosed. If the system detects a new cadence, then a new song version that corresponds to the new cadence can be played. The new song version playback can start in a corresponding position as the location of playback in a currently-playing song version. Each related song version shares one or more characteristics, such as melody, but is different in at least one characteristic, such as tempo.
US09570050B2
A computer implemented system and method provides for responding to an instruction to a print screen instruction by generating and storing an image of user interface components that had been displayed in a display area when the instruction was received; and storing in association with the image original text that had been displayed in the display area and on the user interface components when the instruction was received, where the first image does not include a representation of the original text. Output of the screen copy includes, for example, overlaying some or all of the text, or which some or all can be in modified form, over the image.
US09570026B2
A scan driving circuit includes a pull-up assembly, a pull-up control assembly that drives the pull-up assembly, a pull-down maintaining assembly, and a reference low-level signal. When the current scanning line is inactive, the pull-down maintaining assembly is controlled by a pull-down maintaining signal to make a reference low-level signal be sent to an output end of the pull-up control assembly and the current scanning line.
US09570021B2
The present disclosure provides an array substrate, a flexible display device and an electronic device. The array substrate includes a flexible substrate, and an array layer formed on the flexible substrate. The flexible substrate is bendable, and the array layer includes: signal transmission lines including a plurality of data lines and a plurality of gate lines which are arranged on the flexible substrate in a crisscross manner so as to define a plurality of subpixel regions; and a TFT arranged at each subpixel region and connected to the corresponding data line and gate line. At least portions of the signal transmission lines are formed as bending curves whose travelling direction is parallel to a side of the flexible substrate.
US09570015B2
The present invention discloses a signal conversion device, a signal conversion method and a display device. The signal conversion device includes a gamma conversion unit, a brightness detection unit and a brightness processing unit, wherein the gamma conversion unit is used for performing a gamma conversion process on RGB input signals and generating RGB brightness input values; the brightness detection unit is used for generating a W brightness input value based on RGB proportional coefficients and the RGB brightness input values; and the brightness processing unit is used for generating RGBW output signals based on the RGB proportional coefficients, the RGB brightness input values and the W brightness input value. With the present invention, the brightness of a displayed image can be increased without increasing the power consumption, so that the contrast of the displayed image is increased, and the display quality of the image is also improved.
US09570003B2
An external-compensation sensing circuit, sensing method, and display device. The circuit includes fully-differential operational amplifier, first capacitor, second capacitor and outputting circuit for amplifying induced current; negative input of the amplifier is connected to display screen, positive input thereof is connected to reference voltage, negative output thereof is connected to first control terminal of the outputting circuit, positive output thereof is connected to second control terminal of the outputting circuit; two terminals of the first capacitor are connected to the negative input of the amplifier and an input of the outputting circuit respectively; one terminal of the second capacitor is connected to the output of the outputting circuit and the other terminal is grounded. The invention enables the output voltage to respond rapidly by amplifying induced current with dual outputting stages in the sensing circuit to raise the speed of the external-compensation.
US09570000B2
The present disclosure relates to the field of organic light-emitting display, and provides a pixel circuit, a driving method thereof, an organic light-emitting display panel and a display apparatus, comprising a driving transistor, a first storage capacitor, a collecting unit, a writing unit and a light-emitting unit; wherein, the collecting unit is used for collecting the threshold voltage of the driving transistor and storing the threshold voltage into the first storage capacitor, under the control of the first scan signal; the writing unit is used for storing the data voltage inputted from the input terminal for the data voltage under the control of the second scan signal; and the light-emitting unit is used for emitting lights, driven by the data voltage and a voltage inputted from the input terminal for the controllable low voltage, under the control of the light-emitting control signal. Thus an organic light-emitting device is not affected by the threshold voltage shift of the driving transistor, which may enhance the image uniformity of the organic light-emitting display panel effectively, slow down the decay speed of an organic light-emitting device and ensure the uniformity and a constancy of brightness of the organic light-emitting display panel.
US09569997B2
A display device includes a timing control circuit, a driving circuit, a display panel, and a DC voltage converter. The timing control circuit generates a data signal based on an image signal. The driving circuit generates a first conversion control signal and a second conversion control signal representing a status of the first conversion control signal. The driving circuit generates a driven signal based on the data signal and is powered by a first DC voltage. The display panel is powered by a second DC voltage. The DC voltage converter includes first and second DC voltage conversion circuits. The first DC voltage conversion circuit generates the first DC voltage based on an external voltage. The second DC voltage conversion circuit generates the second DC voltage based on the external voltage. The DC voltage converter executes time-shared control of the first and second DC voltage conversion circuits based on the first and second conversion control signals.
US09569990B2
A system for controlling a smart LED display board capable of compensating for luminance of an LED includes a luminance measurement unit which creates first luminance measurement data obtained by digitizing measured luminance of each LED, an image data input unit which receives first input data about each LED, a comparison unit which selects at least one first LED having a luminance value greater than a preset reference value, and creates a compensation power value compensating for the luminance value of the selected first LED; an image data compensation unit which receives the first input data and the compensation power value and creates second input data in which a power value that is contained in the first input data transmitted to the first LED is changed into the compensation power value; and a drive unit which transmits the second input data to the first LED.
US09569979B2
An embodiment is a physiological and cognitive feedback device, system, and method for evaluating a response of a user in an interactive language learning advertisement. Foreign language lessons are provided at no cost to consumers online in exchange for the consumers' feedback on the products or services embedded in the language lessons. The language lessons may use television advertisements as course material, serving both educational and promotional purposes. Revenues are generated through product placement opportunities as well as consumer survey responses that are a part of the lessons.
US09569978B2
A computer-implemented method includes selecting, by a virtual problem-based learning (PBL) system, information indicative of a medical profile of a patient; accessing, by the virtual PBL system, information indicative of a team of students using the virtual PBL system; generating, by the virtual PBL system and based on the medical profile, an medical PBL schema comprising a medical problem to be solved by the team of students; generating a plurality of sections in the medical PBL schema, with each section promoting solving of the medical problem, and with each section associated with (i) a private work environment for a student to privately analyze the medical problem, and (ii) a shared, anonymous work environment for the students to view analysis performed by other students in solving the medical problem; and transmitting, to one or more client systems used by the students participating in the virtual problem-based learning system, the medical PBL schema.
US09569977B2
In one aspect, the present invention is directed to a responsive book system comprising: a book comprising a detecting system, for detecting a current page from a plurality of detectable pages of the book (i.e., the opened page); a storage, for storing content associated with each of the detectable pages; and one or more remote responders, for playing and/or displaying the content associated with the current page. In another aspect, the present invention is directed to a responsive book method comprising the steps of: detecting the current page in a book from a plurality of pages; and playing and/or displaying, by a remote responder, content associated with the current page.
US09569970B2
Provided are a back-sideways alarming system and an alarming control method, which are capable of reducing the generation of a false alarm by detecting a driving road environment of a vehicle and preventing an unnecessary alarm caused by target information generated at a centerline of a road and an outside of a road. The back-sideways alarming system includes: an image acquiring unit configured to acquire road information of a vehicle; a collecting unit configured to collect target information on targets located around the vehicle; and an electronic control unit configured to recognize a lane based on the road information acquired by the image acquiring unit, reset an alarm area according to information on the recognized lane and the road information, and generate an alarm when the target information is located in the reset alarm area.
US09569967B2
A method and apparatus for warning a driver of a motor vehicle of a predicted collision with a stationary object. A proximity sensor is used to determine a position of an obstacle relative to the vehicle. A steering angle of the vehicle is determined and used to predict a trajectory of the vehicle. A collision zone on the vehicle is identified based on the vehicle trajectory, the collision zone being that spot or location on the vehicle which is predicted to contact the obstacle. A visual display within the vehicle (on the control panel, for example) provides a visual indication to the driver of the position of the collision zone on the vehicle and a predicted trajectory of the collision zone as the vehicle moves in accordance with the steering angle.
US09569956B1
The remote monitoring and control system contains at least a control device, a server device, and a mobile device. The control device periodically collects status/environmental data and delivers these data to the mobile device via the server device. An operator can set up control data on the mobile device. The server device automatically converts the control data set by the operator into appropriate control command by a conversion table corresponding to a specific control device. Therefore, the present invention achieves the goal of using a single mobile device to control multiple devices without mistakenly issuing a false command to a wrong device.
US09569953B2
A motion sensor includes an infrared detector with a first set of detector elements and a second set of detector elements. The motion sensor also includes an optical system to direct electromagnetic energy from a first set of monitored volumes spaced at a pitch in a first direction onto the first set of detector elements and to direct electromagnetic energy from a second set of monitored volumes spaced at the pitch in the first direction onto the second set of detector elements. The second set of monitored volumes have an offset from the first set of monitored volumes in the first direction.
US09569942B2
Systems, devices, and methods are disclosed for securing a theft-susceptible movable object at a selected location. A security system is positioned at a selected location for protection of a theft-susceptible movable object. The security system includes a magnetic field source adapted to generate a magnetic field that is positionally-associated with a movable object. A monitoring device includes a magnetic sensor and is adapted for placement proximate to the selected location. The monitoring device is adapted to take one or more measurements of the magnetic field and to detect alteration in the measurements caused by movement of the magnetic field source relative to the monitoring device when the movable object is moved from the selected location. Upon detecting the alteration in the measurements of the magnetic field, the monitoring device is adapted to output an electronic warning signal indicating that the movable object has moved from the selected location.
US09569940B2
An electronic device has a number of ports that have the same physical form factor and that are receptive to cable insertion. The electronic device also has visual indicators corresponding to the ports. Each visual indicator indicates at least link establishment when a cable has been inserted into its corresponding port and a link has been established. When a cable is removed from a port, the electronic device controls its corresponding visual indicator to identify the port as one from which cable removal has recently occurred.
US09569938B1
In an embodiment, a method of performing video content analysis using transactional data is provided. The method comprises identifying and receiving the transactional data and a segment of video corresponding to a transaction, integrating the transactional data with the segment of video, and analyzing the integrated video to determine an action to take in relation to the transaction.
US09569932B2
A gaming system which provides a persistence game which utilizes predetermined game outcomes. One or more predetermined game outcomes include a persistence game award value. If a predetermined game outcome including such a persistence game award value is selected to be provided to the player in association with a current play of a primary game, the gaming system determines whether to provide this persistence game award value to a player in association with the current play of the primary game, or to store this persistence game award value to be subsequently provided to a player in association with a subsequent play of the primary game. The determination of whether to provide or store the persistence game award value is based on the then current progress of the persistence game (i.e., the current state of an accumulation meter).
US09569923B1
A mobile gaming device is configured for dynamic and location-specific noise suppression. The device samples ambient sounds via a sound receiver, and identifies a profile of ambient sounds and exception sound signatures for a current location. Resident sound emitters are directed to emit sound waves which locally suppress ambient sounds, but local suppression may be disabled for sounds associated with the exception sound signatures. The device may further locally amplify sounds associated the gaming application, and in some embodiments may locally amplify sounds associated with the exception sound signatures, such as for example location-specific alerts. In various embodiments, a plurality of mobile gaming devices in a common location may exchange ambient sound information. In various embodiments, the mobile gaming devices are coupled to a central server which generates a baseline profile for each gaming zone and directs local noise suppression.
US09569920B2
A mobile gaming device may be a player's own personal tablet, smartphone, PDA, etc., with an application program installed via the internet for carrying out a remote gaming session. All gaming functions are carried out by a stationary gaming terminal communicating with the mobile device, such as by using WiFi. The mobile device operates as a user interface. Registration for the mobile device may be via a registration terminal connected in a network with a plurality of gaming terminals. The mobile device may communicate wirelessly with the registration terminal, and the registration terminal then communicates with the played gaming terminal via the network. The mobile device may select to play games offered by any available gaming terminal. The gaming terminals may be gaming machines. The registration terminal may also be a cashing out terminal and print a ticket.
US09569919B2
A gaming terminal has a game process layer for executing different game application and a system process layer for executing machine functions, such as controlling peripherals of the gaming terminal, wherein the game applications and system processes may be implemented using different protocols. The gaming terminal also includes a game server and a control server which may communicate with one another via an integration or translation protocol. The gaming terminal can thus execute generic game code or game code configured in accordance with varying protocols from different vendors rather than a single, proprietary protocol, and can still use a single unique system protocol for controlling the machine functions.
US09569918B2
A server apparatus provides a game which accompanies a resource increasing or decreasing in a game space to a plurality of terminal apparatuses via a network. The server apparatus collects and accumulates the resources from the plurality of terminal apparatuses in the first mode and releases the accumulated resource in the second mode. The server apparatus selectively switches between the first mode and the second mode so as to distribute the resources upon reception of a request from a terminal apparatus.
US09569915B2
A gaming system wherein a second game is triggered once a specific event occurs in a first game.
US09569913B2
A self-aligning memory alloy wire actuator has a memory alloy wire having first and second ends with at least one terminal coupled to one end of the memory alloy wire. The terminal includes two wings and an extended piece connected in the shape of a T. The two wings are disposed on opposite sides of the extended piece and perpendicular to the extended piece. Each wing comprises top and bottom surfaces, a front surface, and an outside end. The top surfaces of the two wings lie on a common top plane and the front surfaces of the two wings lie on a common front plane. The memory alloy wire is coupled to the extended piece of the terminal.
US09569905B2
A method is described that involves creating a private key and a public key cryptographic key pair, generating a unique and random identifier for a voter's vote and accepting an election vote from said voter. The vote and identifier are electronically signed with the private key to create a digital signature. The vote and identifier are provided in a human readable format to the voter.
US09569901B2
An electronic control unit has a main controller that controls a drive of an actuator and a life-extending control instruction section that requests the main controller to change a drive condition of the actuator. The life-extending control instruction section includes a failure estimator that updates and outputs a failure rate based on a state of a control object, a life-extending control database that stores a failure rate reduction control of a monitoring object including the actuator, which reduces the failure rate of the monitoring object, when a failure of the monitoring object is estimated, and a control selector that searches the life-extending control database and selects a candidate control based on the failure rate of the monitoring object outputted from the failure estimator. The control selector requests the main control section to perform a life-extending control that changes an operation condition of the actuator.
US09569895B2
There is provided an information processing apparatus including a judgment unit for judging an anteroposterior relationship between a shot actual object and a virtual object for each part by use of depth information, and a display control unit for displaying a virtual image in which the virtual object is projected to be overlapped on a shot image in which the actual object is shot based on the anteroposterior relationship judged by the judgment unit.
US09569893B2
The general field of the invention is that of Instrument panel or cockpit display systems. The system according to the invention comprises: a first display device comprising a semi-transparent screen upon which a first image is displayed; a second mobile display device mounted on a helmet or augmented reality glasses, the said second device comprising means of displaying a second image collimated in a predetermined visual field; a detection of the orientation and of the position of the helmet in a predetermined reference system; first means making it possible to determine the zone of intersection of the predetermined visual field with the semi-transparent screen; second means making it possible to display in the said zone of intersection of the semi-transparent screen a first specific image, and/or to display in the second display device a second specific image, which are functions of the first image and of the second image.
US09569887B2
The identification and determination of aspects of the construction of a patient's heart is important for cardiologists and cardiac surgeons in the diagnosis, analysis, treatment, and management of cardiac patients. For example minimally invasive heart surgery demands knowledge of heart geometry, heart fiber orientation, etc. While medical imaging has advanced significantly the accurate three dimensional (3D) rendering from a series of imaging slices remains a critical step in the planning and execution of patient treatment. Embodiments of the invention construct using diffuse MRI data 3D renderings from iterating connections forms derived from arbitrary smooth frame fields to not only corroborate biological measurements of heart fiber orientation but also provide novel biological views in respect of heart fiber orientation etc.
US09569880B2
A method, graphics processing unit, and system are described herein. The method for adaptive anisotropic filtering includes calculating a number of ways of anisotropy based on a computed level of detail of a texture map and applying a bilinear low pass filter to a texture map's closest two MIP maps using a processor. An effective number of ways and filter sizes may be computed on each of the closest two closest MIP maps. Additionally, the closest two MIP maps may be sampled at their respective effective number of ways. The method also includes applying a corresponding sized low pass filters to each of the closest two MIP maps, and combining the filtered closest two MIP maps using a weighted sum based on a fractional part of a computed level of detail.
US09569877B2
A method in an electronic device for adapting a graphical effect used in a Graphical User Interface, GUI, comprised in the electronic device for interacting with a user of the electronic device is provided. The electronic device is associated with at least one database. At least one software application using the graphical effect is running on the electronic device. The electronic device is adapted to detect a number of times the at least one application is started, save the detected number of times in the at least one database, and change a time for the graphical effect to be shown based on the detected number of times the at least one application is started, whereby performance of the graphical effect is improved.
US09569860B2
Methods and apparatus are provided for compressing and decompressing image data by producing two sets of reduced size image data, generating a modulation value for each elementary of the area from the image data, the modulation value encoding information about how to combine the sets of reduced size image data to generate an approximation to the image. In one arrangement, a set of index values is generated corresponding to a set of modulation values for each of the respective elementary areas of a group of elementary areas and these are assigned to each respective group and a second set of index values corresponding to one of the set of first index values for each elementary areas is assigned to each first group of elementary areas. These index values are stored for use in deriving modulation data more accurately when decompressing the image data.
US09569859B2
An information handling system includes a three dimensional camera and a processor. The three dimensional camera is configured to capture a three dimensional image. The processor is configured to provide the three dimensional image to be displayed on a display screen of the information handling system, to detect a selection of a pixel within the three dimensional image, and to redefine the selected pixel to be a second pixel. The second pixel has a large disparity within the three dimensional image or its two dimensional counterpart.
US09569844B2
The invention relates to a method for determining at least one applicable path (32) for the movement of an object, especially of a surgical and/or diagnostical device, in human tissue (14) or animal tissue by means of a data set of intensity data obtained by a 3D imaging technique, the applicable path (32) of movement connecting a starting position (28) of the device with a defined target location (30). According to the invention the method comprises the steps: defining the target location (30) of a reference point of the device and choosing at least one possible starting position of the reference point of the device; determining a candidate path of movement (18, 20, 22) between the corresponding possible starting position (24,26, 28) and the defined target location (30); and evaluating the candidate path of movement (18, 20, 22) as being an applicable path (32) depending on information about local intensity extrema and/or intensity variation resulting from the intensity data along the candidate path of movement (18, 20, 22). The invention further relates to a corresponding computer-readable medium, a corresponding computer program product, and a corresponding computerized system.
US09569840B2
A method for selecting a seed area for tracking nerve fibers in a brain includes performing registration of an atlas which shows a plurality of areas which are included in the brain and image data which relates to the brain, displaying a brain area list with respect to the plurality of areas, selecting a first area from the atlas based on a first user input with respect to the brain area list, extracting an area of the image data which corresponds to the first area, as a seed area, based on a result of the registration, and generating a first image which corresponds to the seed area from the image data, and displaying the generated first image.
US09569838B2
An image processing apparatus comprises: detection means for detecting a region corresponding to a diseased part reference region other than a diseased part region in an input image; and identifying means for identifying the diseased part region based on the corresponding region detected by the detection means.
US09569837B2
A label inspection system fixture (1) has a scanner and housing (10) for performing full inline or offline inspection within a printer (20). The fixture (1) comprises a control circuit (5) with a processor within a curved guide plate (6). The scanner (10) communicates with the circuit (5), which in turn communicates with a host computer (VPU). The VPU identifies regions in a scanned label and applies to each region an inspection tool associated with that region. At least some of said tools include a stored training image and associated test data defining said regions and inspection criteria for the regions.
US09569834B2
Methods and devices are disclosed for automated detection of a status of wafer fabrication process based on images. The methods advantageously use segment masks to enhance the signal-to-noise ratio of the images. Metrics are then calculated for the segment mask variations in order to determine one or more combinations of segment masks and metrics that are predictive of a process non-compliance. A model can be generated as a result of the process. In another embodiment, a method uses a model to monitor a process for compliance.
US09569830B2
An image processing method comprising: (a) acquiring a first depth value for a first object in a first image; and (b) altering image effect for the first object according the first depth value when the first object is pasted onto a second image.
US09569828B2
A method and apparatus for the imaging of a labeled biological sample. The method comprises illuminating the labeled biological sample, generating members of a time series of images if the labeled biological sample, generating a plurality of difference images between later members of the time series of images of earlier members of the time series of images and combining the plurality of difference images to generate a final image of the labeled biological sample.
US09569826B2
A radiographic image processing device includes: an image acquisition section that acquires a subject image detected by a shielded detection portion and a non-shielded detection portion; an area information acquisition section that acquires area information which is information for specifying a non-shielded image area and a shielded image area; and a scattered ray suppression section that estimates spreading of scattered rays generated in a non-shielded subject portion, estimates that scattered rays that spread to the non-shielded image area from a shielded subject portion are not present, calculates a scattered ray component in each position in the non-shielded image area as the estimated scattered rays reach each position in the non-shielded image area, and suppresses the scattered ray component in each position in the non-shielded image area according to the calculated scattered ray component.
US09569813B2
A method for tile-based rendering may include verifying a size of a memory available in an apparatus for rendering, and determining a number of buffers required for performing a rendering based on graphics data input, and may further include determining a size of a tile to be used for performing the rendering based on the determined number of buffers and the size of the memory available.
US09569810B2
According to an embodiment, a data embedding apparatus includes a data acquisition unit and an object generation unit. The data acquisition unit acquires first data formed from a first bit string to be embedded in a first object including a first line segment or a first curve. The object generation unit generates a second object, which includes a deformed line segment or a deformed curve having a displacement corresponding to the first bit string with respect to the first line segment or the first curve and in which the first data is embedded, by deforming at least one of the first line segment and the first curve of the first object based on the first bit string.
US09569808B2
A printing apparatus is provided with a plurality of analyzing units, and a control unit. Each of the plurality of analyzing units analyzes each of different pages of print data, and notifies an error in a case that an analysis error occurs. The control unit receives the error notification from the analyzing unit, at which the analysis error occurs, among the plurality of analyzing units. And, the control unit notifies a cancel to another analyzing unit at which the analysis error does not occur. The control unit is further configured to notify, on a condition that a printing of all pages before a page at which the analysis error occurs is completed, the cancel to the another analyzing unit.
US09569804B2
Various of the disclosed embodiments contemplate a computer-implemented method of energy consumption and energy demand management in a building. In accordance with some embodiments, interval energy data of a specific building may be collected with a fixed time interval and paired with local historical weather data and other forms of operational data, as well as financial data including historical utility bills, utility rate structures and billing cycle dates. Paired energy interval data and the local historical weather data may be analyzed according to one or more analytic algorithms.
US09569801B1
Individual users may log into the same online game from multiple different social networking platforms. The disclosed technology provides a way to unite users' accounts such that users that have logged into the online game from different social networking platforms can have their progress in the online game preserved regardless of which social networking platforms the user logged in from. Business intelligence about differences in the user's value when logging in from the different social networking platforms can be determined and incentivizing actions can be performed on the social networking platforms based on the business intelligence.
US09569799B2
Methods, computer-readable media, systems and apparatuses for determining and implementing risk unit based insurance policies are presented. A user may receive a plurality of risk units associated with an insurance policy. The risk units may be stored in a risk unit account associated with the user, the vehicle, etc. During operation of the vehicle, sensor data may be received. The sensor data may provide information associated with driving behaviors of the user, environmental conditions in which the vehicle is being operated, and the like. A consumption rate of the risk units may be determined based, at least in part, on the received sensor data. If a number of risk units in a risk unit account is below a predetermined threshold, a notification may be transmitted to the user and/or a predetermined number of risk units may be automatically added to the risk unit account.
US09569792B2
Aspects of the present disclosure are directed toward a method, a system, and a computer program product for displaying a change event for a web page. The method includes receiving a change event location located on a web page in a pre-deployment environment. The method includes querying a database to return a plurality of change events for the change event location within a duration period. The duration period includes a start time and an end time. The method includes displaying the plurality of change events from the query. The method includes prioritizing the plurality of change events from the query. The method includes selecting an active change event from the plurality of change events based on the priority. The method also includes displaying the active change event to a user.
US09569791B2
Aspects of the present disclosure are directed toward a method, a system, and a computer program product for displaying a change event for a web page. The method includes receiving a change event location located on a web page in a pre-deployment environment. The method includes querying a database to return a plurality of change events for the change event location within a duration period. The duration period includes a start time and an end time. The method includes displaying the plurality of change events from the query. The method includes prioritizing the plurality of change events from the query. The method includes selecting an active change event from the plurality of change events based on the priority. The method also includes displaying the active change event to a user.
US09569788B1
A method executes at a server system with one or more processors and memory. The server receives demographic information for a plurality of household members. The demographic information includes at least age and gender. The server receives web activity information for the household. The server identifies one or more web activity sessions from the web activity information and selects one of the web activity sessions. The server identifies one or more web sites visited during the selected web activity session and accesses demographic skew data for at least a subset of the web sites visited. The demographic skew data for a web site identifies fractions of visitors to the web site from predefined demographic segments. The server associates a household member with the web activity session at least in part by correlating the demographic skew data of the web sites visited with the demographic information of the first household member.
US09569782B1
A computer-implemented method and system for automated customer business impact assessment upon a problem submission. A problem description of a problem with a product is received from a customer using the product. The problem description is automatically analyzed using natural language processing (NLP) to identify an issue including a subject. The issue and subject is compared with usage information stored in a repository for the customer. The method and system include predicting an impact of the problem to the customer, and prioritizing a solution to the problem based on the predicted impact.
US09569781B2
An analysis is performed on first and second product information to determine a relationship between a first product and a second product. In response to a first notification from a first backend system, a first message is transmitted to a mobile device of the user indicating that the change of a first activity is needed. It is determined whether a modification of a second activity is needed based on the relationship information of the first product and the second product and in response to determining that the modification of the second activity is needed, a second message is transmitted to the mobile device, indicating a possible modification of the second activity and offering a list of one or more options to modify the second activity. A live communications session is established between the user and a support agent of the server to discuss the possible modification of the second activity.
US09569779B2
Detection of fraud in financial transactions is facilitated. A financial transaction is initiated by a user, and based on the financial transaction, information is obtained by an electronic device of the user. Using the information, the electronic device evaluates a set of rules personalized for the user; the set of rules to be used to determine whether the financial transaction is to be approved for the user. The electronic device provides an initial indication, based on the evaluating, of whether the financial transaction is to be approved.
US09569778B2
This disclosure is directed to methods and systems for managing difficulty of use and security for a transaction. A transaction manager operating on a computing device may determining a range of possible steps for a transaction comprising security measures available for the transaction. The transaction manager may identify a threshold for a security metric to be exceeded for authorizing the transaction, the security metric to be determined based on performance of steps selected for the transaction. The transaction manager may select for the transaction at least one step from the range of possible steps, based on optimizing between (i) a difficulty of use quotient of the transaction from subjecting a user to the at least one step, and (ii) the security metric relative to the determined threshold.
US09569776B2
A registered provider device encrypts provider input related to a transaction between the provider device and one of many registered user devices to create an encrypted one-time-use provider code (the encryption is performed using an encryption key produced, in part, using a uniquely sequenced number generated by a sequencer maintained by the provider device). Similarly, the user device encrypts user input to create an encrypted one-time-use user code using an encryption key produced, in part, using a uniquely sequenced number generated by a user sequencer maintained by the user device. The provider and user devices independently transmit their different encrypted one-time-use codes to an intermediate entity, which decrypts the encrypted codes. This decryption is performed using one-time-use encryption keys produced using sequencers maintained by the intermediate entity, and this decryption generates an authorization request. The intermediate entity obtains an authorization decision regarding the authorization request from the authorization entity.
US09569775B2
The method for authenticating a mail order or telephone order transaction according to the present invention includes receiving authentication information from a cardholder, providing authentication information to an issuer, and determining whether the authentication information is valid. If the authentication information is valid, the issuer informs the merchant that the transaction is valid. In an embodiment, the issuer may not supply a personal assurance message and/or other confidential cardholder information previously supplied by the cardholder in response to the authentication information.
US09569760B2
A user's checkout information is stored for a certain amount of time, e.g., 10 minutes, after checkout, and the user is given the option of selecting a button to add one or more items for purchase and completing the purchase by adding the additional item(s) and approving the payment, without having to go through a complete checkout flow again.
US09569754B2
Embodiments of the present invention address deficiencies of the art in respect to calendaring and scheduling and provide a novel and non-obvious method, system and computer program product for providing a unified view of aggregated calendar data in a C&S system. In one embodiment of the invention, a method for providing a unified view of aggregated calendar data for an event in a calendar view can be provided. The method can include selecting an event in the calendar view, aggregating calendar data for the event relating to all invitees for the event, computing statistics for the aggregated calendar data, and rendering a display of the computed statistics proximate to the selected event in the calendar view.
US09569753B2
A method for transmitting messages in a publish/subscribe message system. The method also includes: receiving, at a first relay, a subscription request from a first client; recording, at the first relay, subscription information of the first client based on the subscription request; receiving, at the first relay, a publication request from a second client, wherein the publication request includes a message; and transmitting the message to the first client.
US09569747B2
A system and method for monitoring shelf inventory that combines bar code and RFID technologies to permit electronic data entry of item shelf assignments and real time reporting of item removal from display/dispensing storage shelves.
US09569746B2
A method whereby a customer may purchase footwear through a remote communication channel, and be assured that the purchased footwear will properly fit upon delivery. The customer purchases footwear by designating the last that is used to construct the footwear. A customer may identify a particular last based upon careful measurement of the customer's feet. A customer may also identify a last based upon previous experience with footwear constructed using the last.
US09569737B2
Method and tools for creating and evaluating a set of system blueprints pertaining to the delivery of a system or a project. Each blueprint is an architecture design/specification that enables analysis of each blueprint, families of blueprints and relationships between blueprint layers. A user can create various system blueprints based on data from existing databases containing requirements, solutions, and deployments of a system or project. After creating each blueprint, users may view the blueprint to visually detect problems and further revise the blueprint. In addition, for each type of blueprint, the user can evaluate the blueprint against various metrics and criteria related to requirements, solutions, and deployments and view the evaluation results.
US09569729B1
A computer readable medium for analyzing and predicting the future behavior of organizations is disclosed. An embodiment of this invention is comprised of one or more repositories of data which involve comments or other actions by actors with some kind of relationship to a target organization, a repository of metadata relating to this data, a repository of updatable models of organizations, a natural language parsing engine, and an engine for generating and comparing the organizational models.
US09569728B2
A computer-implemented content suggestion engine provides content suggestions to a requesting user based on information about content items that other users may have independently categorized or organized into folders within a content repository. Embodiments of the method comprise a content repository having a plurality of content items, where each content item is associated with one or more user-created folders. Embodiments further comprise receiving, via a network, a suggestion request for suggested content, where the suggestion request identifies a first content item for which suggestions are sought. Other content items in the content repository are then identified as potential suggestions based on the application of a formal relationship between the first content item and the potential suggested content items. One or more of the potential suggested content items may then be provided in response to the suggestion request via the network.
US09569727B2
A social networking system receives messages from users that include hashtags. The social networking system may use a natural language model to identify terms in the hashtag corresponding to words or phrases of the hashtag. The words or phrases may be used to modify a string of the hashtag. The social networking system may also generate computer models to determine likely membership of a message with various hashtags. Prior to generating the computer models, the social networking system may filter certain hashtags from eligibility for computer modeling, particularly hashtags that are not frequently used or that more typically appear as normal text in a message instead of as a hashtag. The social networking system may also calibrate the computer model outputs by comparing a test message output with outputs of a calibration group that includes positive and negative examples with respect to the computer model output.
US09569725B2
Techniques for enforcing policies. A set of data is stored in one or more data stores. A plurality of semantic concepts for an ontology are defined and a map is constructed from the set of data to the concepts. The map is executed in order to transform data from the set of data to a second set of data. The second set of data is stored according to the ontology. The second set of data is reasoned in order to determine compliance with one or more policies.
US09569720B2
A wearable device is provided with a wearable device structure. The wearable device has a first end and a second end. A plurality of magnets is positioned at the first and second ends that provide for coupling of the first end to the second end of the wearable device. At least a portion of the magnets are magnetized through their widths or thickness, e.g., depth. ID circuitry is provided at a surface or an interior of the wearable device.
US09569719B2
A wearable device is provided with a wearable device structure. The wearable device has first end and second ends. A plurality of magnets is positioned at the first and second ends that provide for coupling of the first end to the second end of the wearable device. At least a portion of the magnets have a first section with a first polarity and a second portion with a second polarity. ID circuitry is at a surface or an interior of the wearable device structure.
US09569718B2
A metal card or a hybrid metal-plastic includes an acrylic resin protective clear-coat layer and/or a “hard” nano-particle top-coat layer overlying any exposed metal surface in order to insulate the metal and reduce the likelihood of an electrostatic discharge (ESD) or a short circuit condition. In a particular embodiment the “hard” nano-particle top-coat layer overlies the clear coat layer. The dual stage protective layers which include a clear-coat layer and a top-coat ensure that the problem associated with an ESD and/or a short circuit condition is minimized. In addition, the dual stage protection imparted to a card by forming a clear-coat layer and a top-coat layer ensures that any card surface treatment or card decoration is protected over time from excessive wear or scratching due to use in conjunction with a POS device and/or handling.
US09569713B2
To provide a semiconductor device that is capable of displaying data even when a radio signal is not supplied. The semiconductor device includes an antenna, a battery, a sensor, a nonvolatile memory, a first circuit, and a second circuit. Power supplied from the antenna is converted into first power via the first circuit. The battery stores the first power and supplies second power. The sensor performs sensing with the second power. The nonvolatile memory stores analog data acquired by the sensor. The second power is used to store the analog data. The second circuit converts the analog data into digital data with the use of the first power. The nonvolatile memory preferably includes an oxide semiconductor transistor.
US09569708B2
A writing device comprises a carrying section configured to carry a plurality of tags written with information by way of wireless communication, a writing section configured to write the information into the tags which are carried to a set writing position by the carrying section by way of wireless communication, an accepting section configured to accept the input of the writing position where the writing section writes the information into the tags, when the information is written into the tags which are carried by the carrying section and a correcting section configured to correct the set writing position according to the writing position where the accepting section accepts the input.
US09569704B2
An imaging apparatus includes: an image obtaining unit which obtains print target data to be printed; a second print size specifying unit which specifies a print size for printing the obtained print target image on one or more print media; a print medium size specifying unit which specifies a size of the print media on which the print target data is printed; and a division judging unit which judges whether or not the print target data is divided into the plural print media when being printed, on the basis of the specified print size and the specified size of the print media.
US09569703B2
A reading process is performed to read data of each area, which is divided from image data, from a buffer storing the image data to be performed on a predetermined image process. A transmitting process is performed to transmit the read data of the area to an image processor. A reception process is performed to receive data generated in the predetermined image process from the image processor. A parameter for a writing process is set based on an area size of the received data. A writing process is performed to write the received data to the buffer by data transfer using direct memory access (DMA).
US09569694B2
An image processor (10) has a window selector for choosing a detection window within the image, and a self similarity computation part (40) for determining self-similarity information for a group of the pixels in any part of the detection window, to represent an amount of self-similarity of that group to other groups in any other part of the detector window, and for repeating the determination for groups in all parts of the detection window, to generate a global self similarity descriptor for the detection window. A classifier (50) is used for classifying whether an object is present based on the global self-similarity descriptor. By using global self-similarity rather than local similarities more information is captured which can lead to better classification. In particular, it helps enable recognition of more distant self-similarities inherent in the object, and self-similarities present at any scale.
US09569692B2
Example methods, apparatus, systems to perform context-based image recognition for consumer market research are disclosed. Disclosed example methods include comparing a first subset of feature points in a first region of interest of a reference image with a first subset of feature points of a first image residing within a first region corresponding spatially to the first region of interest and located at a first location in the first image to determine a first match value. Disclosed example methods also include, in response to determining the first match value satisfies a first threshold, comparing a second subset of feature points in a second region of interest of the reference image with a second subset of the feature points of the first image residing within a second region of the first image corresponding spatially to the second region of interest to determine a second match value.
US09569690B2
Feature extraction of image data using feature extraction modules. The feature extraction modules may be provided in an architecture that allows for modular, decoupled generation and/or operation of the feature extraction modules to generate feature data corresponding to image data. In this regard, the feature extraction modules may communicate with a file system storing image data and feature data by way of a common interface format. Accordingly, regardless of the nature of the execution of the feature extraction module, each feature extraction module may be communicative by way of the common interface format, thereby providing a modular approach that is highly scalable, flexible, and adaptive.
US09569689B2
Image processing for productivity applications is provided. An image may be received by a computing device. The computing device may detect the edges comprising the received image and adjust the image based on a skew state of the detected edges. The computing device may then process the adjusted image to correct imbalances. The computing device may then assign an image classification to the processed image. The computing device may then adjust the processed image based on the assigned image classification.
US09569683B2
In various embodiments, a system and method for manufacturing and using an optical enhancement assembly in combination with an image-capturing device are presented. In example embodiments, the optical enhancement assembly is affixed over an aperture on the image-capturing device using a securing agent. Light is allowed to travel through the optical enhancement assembly and into the aperture of the image-capturing device such that the light can be recorded as a still image or video. The optical enhancement assembly includes at least a unique fractalized diffraction pattern that impacts light traveling into the aperture and causes a unique diffraction effect on the image or video recorded by the image-capturing device.
US09569681B2
A system and method for cropping a license plate image to facilitate license plate recognition by obtaining an image that includes the license plate image, dividing the image into multiple sub-blocks, computing an activity measure for each sub-block; determining an activity threshold, determining that a sub-block is an active sub-block by comparing the activity measure for the sub-block with the activity threshold, generating a second image of the license plate information, where the second image includes the active sub-block, and obtaining the license plate information based on the second image.
US09569676B2
A computer implemented system and method for extracting and recognizing alphanumeric characters from traffic signs is envisaged. A camera present in the system is adapted to be mounted on the vehicle for capturing images of traffic signs. The system then gives a region of interest (ROI) within the frame of the captured image, from where the alphanumeric characters are extracted and enhanced for recognition. For recognizing the enhanced alphanumeric characters, the image is converted to binary image and morphological thinning technique is applied on it. The space then obtained between two alphanumeric characters thus helps in extracting the characters and recognizing them independently from the captured image. For each extracted alphanumeric character is re-sized to a specified size and is recognized with the help of white pixels count. Once the alphanumeric characters are recognized they are displayed on a display.
US09569675B2
A three-dimensional object detection device has an image capturing unit, detection area setting unit, a three-dimensional object detection unit and a lens state assessment unit. The image capturing unit has a lens for capturing images behind a vehicle. The detection area setting unit sets a detection area behind the vehicle. The three-dimensional object detection unit detects a three-dimensional object that is present in the detection area based on the acquired images. The lens state assessment unit detects if the lens is in a wet state. When a determination is made by that the lens is in a wet state, the detection area setting unit changes a position of the detection area from a first detection area, which is first set as the detection area to a second detection area, in which a display area for a driving lane marker on a driving lane side of the vehicle is removed.
US09569671B1
A system and method for detecting a man overboard incident on structures such as cruise vessels and oil rigs. The system includes at least two opposed imaging devices which record video streams of a detection cuboid within an overlapping region of view volumes for the imaging devices. The imaging devices are located at the lowest deck of the structure and monitor a fall that passes through the cuboid. Identified objects within the video streams are paired, their conformance is determined, and real world information such as size, trajectory, and location is determined.
US09569669B2
An apparatus includes a security location module that tracks a location of a user. The user has a heads-up display with a display that allows viewing by the user of items along with electronic display images. An object identification module identifies an object for tracking using cameras. A selection module selects the identified object for tracking, an object location module identifies a location and direction information of the selected object and an alert module sends the location and the direction information of the selected object to the heads-up display. A display module identifies the selected object in the heads-up display of the user when the object is in the field of view of the heads-up display, or provides instruction on the heads-up display to direct the user to move the heads-up display so that the selected object is in the field of view of the heads-up display.
US09569662B1
Image recognition and parsing techniques are provided herein. In the described examples, an input image, such as an image of a document (e.g., a scanned document), can be received. Scan mark candidates in the input image can be identified that correspond to blueprint scan marks for a stored set of form blueprints. The blueprint scan marks can indicate form entry areas or other features of a form associated with the form blueprint. Identified scan mark candidates can be compared with the corresponding blueprint scan marks. Based on the comparing, it can be determined that at least some of the scan mark candidates are confirmed scan marks. Based on the confirmed scan marks, one form blueprint can be identified that corresponds to the input image. Information can be extracted from the input image, for example by optical character recognition, based on the form blueprint to which the input image corresponds.
US09569659B2
A system and method for tagging an image of an individual in a plurality of photos is disclosed herein. A feature vector of an individual is used to analyze a set of photos on a social networking website to determine if an image of the individual is present in a photo of the set of photos. Photos having an image of the individual are tagged preferably by listing a URL or URI for each of the photos in a database.
US09569654B2
A sensing module, such as a fingerprint sensing module, is disclosed. The sensing module includes a rigid substrate having a cutout, a flexible substrate attached to the rigid substrate, an image sensor including conductive traces formed on the flexible substrate, and a sensor integrated circuit that is connected to the conductive traces of the image sensor. The sensor integrated circuit is disposed in the cutout of the rigid substrate. The sensor integrated circuit can be fully enclosed in the cutout or disposed between the flexible substrate and the rigid substrate. The flexible substrate can also have a sensing side and a circuit side, where the conductive traces are formed on the circuit side and a finger is configured to be received from the sensing side. The conductive traces on the flexible substrate can also form a plurality of sensor gaps between respective image drive plates and image pickup plates.
US09569650B2
A method and system for applying and reading a fractal image to and from a plurality of objects to act as an identification label is provided. The system includes a printer for printing a fractal pattern to the plurality of objects and a reader for reading the printed fractal pattern. Such a fractal image is robust to printing and imaging difficulties and inconsistencies, and is difficult to copy, thus defending against counterfeiting.
US09569643B2
Mobile devices typically have some form of audio capabilities designed to be operated by the device's user, for example to place phone calls; however, if a device is misplaced or stolen, the user may wish to operate those audio capabilities remotely. Methods are provided for detecting that a security event has occurred on a portable electronic device and then establishing an audio transmission between the device and one or more clients, and in some embodiments, sending a command to initiate the audio transmission. The detection of a security event may be based on, for example, detecting that the device has been turned on, detecting movement of the device, detecting that an incorrect password has been entered, the device camera has been used, contacts have been added or deleted, the SIM card as been removed or replaced, application programs have been installed or uninstalled from the device, or uncharacteristic behavior has been detected.
US09569642B2
A system comprising a platform protected by an always-on always-available security system is described. In one embodiment, the system includes a risk behavior logic to detect a potential problem, a core logic component to provide logic to analyze the potential problem and to move the platform to a suspecting mode when the potential problem indicates a theft suspicion, and the security action logic, to send periodic alerts to a security server when the platform is in the suspecting mode, the alert including movement related data, such that the security server can take an action to protect the platform.
US09569641B2
A processing system includes a processor and a temperature security module coupled to provide a temperature tamper signal to the processor. The temperature security module includes a shelf mode trim value, an operating mode trim value, and a programmable temperature trim value. One of the programmable temperature trim value, the shelf mode trim value, and the operating mode trim value, is used based on a deployment mode of the processing system to set a temperature monitor trim value.
US09569640B2
A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined. Once a tampering attempt is detected, responses on the memory device include disabling one or more memory operations, generating a mock current to emulate current expected during normal operation, and erasing data stored on the memory device.
US09569639B2
A non-transitory machine-readable storage medium encoded with instructions for execution by a keyed cryptographic operation by a cryptographic system mapping an input message to an output message, wherein the cryptographic operation includes at least one round including a non-linear mapping function configured to map input data to output data, including: instructions for determining that the input data has a diversification number less than a diversification level threshold number; instructions for remapping the input data to a remapped input data, wherein the remapped input data corresponds to an input data having a diversification number greater than or equal to the diversification threshold value, and instructions for inputting the remapped input data into the non-linear mapping function to obtain output data.
US09569631B2
A method and apparatus for configuring an electronics device. The method includes receiving, by the electronics device, a request for a command to perform a predetermined operation by the electronics device and sending the command in response to receiving the request. The electronics device then receives a signature based upon the command, whereupon the electronics device verifies the signature by the electronics device and, following an affirmative verification, executes the command for performing the predetermined operation. In this way, the electronics device may be reconfigured remotely without knowledge of the particular command for performing the predetermined operation by the electronics device.
US09569629B2
System, computer program product, and method embodiments for communication between a kernel operational on a storage subsystem and a key manager (KM) through a hardware management console (HMC) to provide encryption support are provided. In one embodiment, an event request is initiated by the kernel to the KM to execute an event flow. Pursuant to a communication request by the kernel to the HMC, a socket of the HMC is opened along a communication path between the KM and the kernel according to an event flow type selected by the KM for the event flow. Data including a data payload is sent by the KM to the kernel, the data payload corresponding to the selected event flow type.
US09569613B2
Various embodiments are generally directed to an apparatus, method and other techniques to determine a valid target address for a branch instruction from information stored in a relocation table, a linkage table, or both, the relocation table and the linkage table associated with a binary file and store the valid target address in a table in memory, the valid target address to validate a target address for a translated portion of a routine of the binary file.
US09569612B2
A hardware-implemented method to support three desirable software properties: encapsulation, referential integrity/capabilities, and transactions. These properties in turn may be used to support software correctness, specifically the enforcement of invariants, and computer security, specifically protecting parts of programs from each other within a single process.
US09569598B2
An approach for managing licenses for software installations on virtual machine (VM) instances in a networked computing environment (e.g., a cloud computing environment) is provided. Specifically, in one example, data (e.g., real-time and/or historical) pertaining to usage of a set of software installations on a set of (VM) instances in the networked computing environment is collected. When a request is received (e.g., from a requester) for a license for a particular software installation of the set of software installations, it is determined whether the license is available. If not, it is then determined whether the license is obtainable based on the collected data and a current configuration of the networked computing environment. Then, responsive to the license being obtainable, the requested license may be allocated.
US09569597B2
There is provided an information processing apparatus, including a storage section which stores a first image, which is an image of a format requiring license information in reproduction, to which reproduction is performed by a reproduction apparatus after being acquired, a conversion section which converts the first image into a second image of a format not requiring license information in reproduction, which is an image with content the same as content of the first image, and a distribution section which distributes the second image to the reproduction apparatus to be reproduced, during acquisition of the first image.
US09569596B2
Disclosed is a computer program that provides a secure workflow environment through a cloud computing facility, wherein the secure workflow environment may be adapted to (1) provide a plurality of users with a workspace adaptable to provide secure document management and secure communications management, wherein the users comprise at least two classes of user, including a participant and a subscriber, the subscriber having control authority within the workspace that exceeds that of the participant and the participant having control over at least some of the participants own interactions with the workspace, (2) maintain a secure instance of each communication provided by each of the users such that each communication can be managed, (3) maintain a secure instance of each document interaction provided by each user such that each interaction can be managed; and extending the secure workflow environment to the users through a secure network connection.
US09569590B2
The present invention relates to an apparatus for measuring biological information supporting multiplex communication. The apparatus for measuring biological information, according to one embodiment of the present invention, comprises: a measuring portion for measuring biological information through a biosensor; a data communication portion for transreceiving the biological information that is measured with an external device through a wireless communication network, which supports a client mode and an AP mode; and a control portion for accessing a communication network by controlling the client mode or the AP mode in a WiFi module. The present invention can transmit data to the external device through a connected AP by operating a wireless communication module in the client mode, or communicate data with the external device through a communication module of terminals, which connect by self-switching to the AP mode when the connected AP does not exist.
US09569580B2
A method for adding an electrical interconnection within a three-dimensional integrated circuit (3-D IC) is disclosed. The method may include creating, within a design file of a 3-D IC that specifies a layout for a first chip of the 3-D IC, design data corresponding to a set of through-silicon via (TSV) reservation areas. The method may also include receiving an engineering change order (ECO) and releasing, in response to the ECO, at least one TSV reservation area for reuse. The method may also include adding, by re-using at least one TSV reservation area, an electrical interconnection within the design file of the first chip of the 3-D IC.
US09569579B1
Systems and methods for automatically generating a Network on Chip (NoC) interconnect architecture with pipeline stages are described. The present disclosure includes example implementations directed to automatically determining the number and placement of pipeline stages for each channel in the NoC. Example implementations may also adjust the buffer at one or more routers based on the pipeline stages and configure throughput for virtual channels.
US09569576B2
A mask data generating method for generating data of a plurality of masks used in a plurality of exposures in which exposure light is irradiated onto a substrate using a mask, and then exposure light is irradiated onto the substrate using another mask. The method includes the steps of obtaining data for a pattern including a plurality of pattern elements, determining formulation of a disposition limitation condition for the pattern elements, analyzing the distance between the pattern elements, determining formulation of the distance limitation condition, and applying a first variable configured to express a number of pattern divisions and a second variable configured to express a distance related to all pattern elements in a cost function and thereby dividing the pattern.
US09569572B2
This application discloses a system implementing tools and mechanisms to selectively load design data for logical equivalency check. The tools and mechanisms can identify a hierarchy of modules in a circuit design, perform a depth-first search of the hierarchy of modules starting with a root module to identify a subset of modules to parse, and selectively parse the subset of the modules in the circuit design. The tools and mechanisms can utilize the parsed subset of the modules to determine logical equivalence of the circuit design with at least another circuit design.
US09569569B1
A target data storage system is simulated. A source configuration is received. First activity data is received representing workload for the source configuration. A target data storage system configuration for one or more target data storage systems is created. The target data storage system configuration is modeled including determining a simulated workload for components of the target data storage system configuration based on the first activity data. A utilization map is displayed in a user interface indicating component level utilizations of components of the target data storage system configuration based on the simulated workload. A data movement optimization for the target data storage system configuration is simulated. A second utilization map is displayed indicating updated component level utilizations for the target data storage system configuration which have been revised to model the simulated data movement optimization for the target data storage system configuration.
US09569565B2
Embodiments of the invention provide a computer-implemented system and method for generating a three-dimensional rooftop model. In some embodiments, the system and method can process stereo aerial images to generate a stereoscopic image, and generate a point-cloud field from at least a portion of the stereoscopic image. Some embodiments of the computer-implemented system and method can generate three-dimensional rooftop models using polylines and polygons derived from the point-cloud field. In some embodiments, a rooftop solar energy potential can be determined using a rooftop area calculated using the system and method. In some further embodiments, a rainwater run-off potential can be calculated using a measured rooftop area calculated using the computer-implemented system and method. In some embodiments, the system and method can display at least one building including at least one rooftop including one or more rooftop portions including a display of a solar potential and/or a rainwater runoff potential.
US09569550B1
A system includes an application programming interface, an indexer, a security unit and at least one search engine. The application programming interface uploads user-selected custom content from a first user. The indexer indexes the custom content to produce a first search index. The security unit authenticates a user and the at least one search engine receives a search query from the user, searches the first search index based on the search query, and searches a second search index based on the search query and based on results of the user authentication, where the second search index is different than the first search index.
US09569549B1
Content items, such as e-books, audio files, video files, and the like, may be tagged as associated with a location based on observing the locations at which users access the content items. A rich set of tag data may be gathered by additionally observing such things as the date and time when users access the content items as well as allowing the users to tag the content items with comments or ratings. A fine granularity of tagging may be achieved by associating the tags with specific portions of the content items. Content recommendations based on the tags may be provided to other users when those users are in approximately the same location.
US09569548B2
A system highlights search terms in documents distributed over a network. The system generates a search query that includes a search term and, in response to the search query, receives a list of one or more references to documents in the network. The system receives selection of one of the references and retrieves a document that corresponds to the selected reference. The system then highlights the search term in the retrieved document.
US09569538B1
Content of a work of authorship can be ingested using natural language processing (NLP). Content displayed on an Internet forum can be ingested using NLP. A relationship between the content of the work of authorship and the content displayed on the Internet forum can be identified based on the ingested content of the work of authorship and the ingested content displayed on the Internet forum. Information associated with the work of authorship can be caused, based on the identified relationship, to be displayed on the Internet forum such that the information is visually-associated with the displayed content.
US09569533B2
There is provided a system and method for visual search in a video media player. There is provided a computing device for performing a visual search in video files comprising a display, a memory, a video media player application in the memory, and a processor configured to store into the memory search terms by allowing a user to visually select objects as search terms using a user interface on the display, initiate a search using the search terms, obtain search results comprising time offsets and play durations within the video files, each play duration containing at least one frame corresponding to the search terms, and display navigational controls in the user interface for presenting the search results, including selectable graphical thumbnail images or preview videos. A user can select objects via outlined, highlighted, or otherwise visually identified objects in a video frame, the selecting enabled by associated search metadata.
US09569525B2
Methods, systems, and articles of manufacture for entity-level technology recommendation are provided herein. A method includes searching a first query against a first corpus of documents to determine a set of documents matching an entity of interest identified in the first query, generating a list of technologies that (i) appear within the content of the set of documents and (ii) are associated to the entity of interest, searching a second query against a second corpus of documents to determine a set of documents representing a technology recommendation for the entity of interest, wherein said second query is based on one or more selected technologies from the list of technologies, and outputting the set of documents representing a technology recommendation to a user and/or a display.
US09569520B1
A device may receive an instruction to classify software. The device may identify a group of one or more user interfaces associated with the software based on receiving the instruction to classify the software. The device may determine a group of one or more user interface signatures associated with the group of one or more user interfaces. A user interface signature may include information, associated with a user interface in the group of one or more user interfaces, that may be used to classify the software. The device may generate information that identifies a classification of the software based on the group of one or more user interface signatures and based on known signature information. The known signature information may include information that corresponds to a correct software classification. The device may output the information that identifies the classification of the software.
US09569512B2
The replication of data between a source system and a destination system is disclosed. After having calculated a signature for a fragment of data to be replicated, the source system transmits same to the destination system. The latter determines whether or not the signature is known, e.g., whether or not a fragment is associated with the signature. If so, the data to be replicated is reconstructed (with respect to fragment in question). If not, a message indicating that the signature is unknown is transmitted to the source system, which then transmits the corresponding fragment to the destination system. The latter stores and reconstructs the data to be replicated (with respect to the fragment in question).
US09569509B2
Techniques for optimizing result presentation for a database query. A database query is received. The database query is performed with a clause indicating one or more offset values to be used in displaying results from the database query. The one or more offset values indicate a subset within the results from the database query to be presented. An order is imposed on the results from the database query. The subset is presented as determined by the one or more offset values.
US09569491B2
A system includes first and second data stores, each store having a set of materialized views of the base data and the views comprise a multistore physical design; an execution layer coupled to the data stores; a query optimizer coupled to the execution layer; and a tuner coupled to the query optimizer and the execution layer, wherein the tuner determines a placement of the materialized views across the stores to improve workload performance upon considering each store's view storage budget and a transfer budget when moving views across the stores.
US09569485B2
Embodiments of the present invention relate to a method, computer program product and system for optimizing database transactions configured for receiving a query. The query specifies a set of predicates supplied to the query and a minimal number of predicates to be satisfied for the query to be true. An operation using the query is performed on a repository that is stored in a computer readable storage medium. A set of results satisfying the minimal number of predicated is rendered.
US09569484B2
According to one embodiment of the disclosure, a query generation system generally includes an element rank and inference engine in communication with a computing system and a user interface. The element rank and inference engine is operable to receive a user supplied element from the user interface, the user supplied element being associated with a first filter criterion. The element rank and inference engine is also operable to create, using the first filter criterion, at least one second element and rank according to their relative importance, the at least one first element and the at least one second element according to their associated first filter criterion and second filter criterion. Next, the element rank and inference engine may output the at least one first filter element and the second filter element to the computing system.
US09569482B2
When altering records in a repository of information to add an attribute that has a non-NULL default value and a corresponding constraint to the records, no update record is issued and instead, the existing records are essentially treated as having a NULL value for the attribute being added. To compute a query over the records to which the attribute has been added, a value is generated for rows that hold NULL values for the attribute in which the value in which the NULL values held therein are translated to the default value.
US09569478B2
Disclosed are some examples of systems, apparatus, methods, and computer program products related to automatically causing a following relationship to be established in an enterprise social networking system between a user and one or more customer relationship management (CRM) records. In some implementations, a workflow is configurable at least in part by one or more selections defining one or more conditions. Responsive to determining that one or more properties associated with a first CRM record satisfies the one or more conditions, a user is caused to follow the first CRM record. The following enables or causes updates associated with the first CRM record to be shared in a feed of the enterprise social networking system, where the feed can be provided to the user's device. Information based on the following of the first CRM record by the user can be displayed at the device.
US09569469B2
Methods and systems are provided for populating a database with data associated with a specific task. The method comprises creating a work package specification for a work package associated with the specific task, creating a task specification within the work package specification, creating a view specification within the task specification, and creating a task network comprising tasks that when performed in a desired sequence populates the database with the data associated with the specific task.
US09569466B1
A system and method for providing offline asynchronous user activity in a player versus player online game is disclosed. A client computing platform associated with a first user may maintain a connection to the game server that hosts a game space at which an online game takes place. The client computing platform may include a game state repository that stores a game space for the game state and a game logic repository that stores game logic for the online game. When the client computing platform disconnects from the game server, an expression of the game space is maintained at the client computing platform. While disconnected, the client computing platform may receive instructions for one or more actions to be taken in the game space and may execute the actions in the online game. When a connection is established with the game server, the executed actions may be verified.
US09569465B2
An image recognition approach employs both computer generated and manual image reviews to generate image tags characterizing an image. The computer generated and manual image reviews can be performed sequentially or in parallel. The generated image tags may be provided to a requester in real-time, be used to select an advertisement, and/or be used as the basis of an internet search. In some embodiments generated image tags are used as a basis for an upgraded image review. A confidence of a computer generated image review may be used to determine whether or not to perform a manual image review.
US09569463B1
A pre-fetching map data system and method identifies a subset of map data to corresponding to one or more points of interest to be displayed on the map. The map data is stored on a remote map database and in the form of map data tiles. The system identifies those map data tiles that correspond to the subset of map data corresponding to the one or more points of interest, where the identified pre-fetch map data tiles are sent from the remote database to a client device for cache storage. The pre-fetch map data tiles are identified using a variable map tile radius, which when extended from the points of interest defines the map tiles that qualify as pre-fetch map data tiles. The tile radius can be fixed or dynamically adjusted and changes across different map zoom levels.
US09569453B1
A computer-implemented method for simulating file system instances may include identifying a file system to host a simulated file system instance. The computer-implemented method may also include intercepting attempts to read from the file system. The computer-implemented method may further include, for each intercepted read attempt, generating data to fulfill the intercepted read attempt. The computer-implemented method may additionally include fulfilling the intercepted read attempt with the generated data. Various other methods, systems, and computer-readable media are also disclosed.
US09569445B2
In an approach for creating an asset, a computer receives a selection of at least one asset element and determines whether one or more asset elements are associated with the selected asset element. In response to determining one or more asset elements are associated with the selected asset element, the computer determines, based, at least in part, on one or more linkage rules, whether one or more of the associated asset elements are in the asset. Furthermore, in response to determining that at least one of the associated asset elements is in the asset, the computer generates an asset map. The asset map, generated by the computer for the asset, depicts the linkage rules, the selected asset elements, and the associated asset elements in the asset.
US09569444B1
A computer-implemented method for determining whether to perform a pushdown may include receiving a request for analytics to be performed by an analytics platform on data stored in bulk storage. An operation may be identified as a candidate for a pushdown, where the operation is selected from among one or more operations to be performed for fulfilling the request. The pushdown would require the operation to be performed at the bulk storage. The data may be sampled by reading one or more samples of the data, where the one or more samples are a fraction of the data. The operation may be performed, by a computer processor, on the one or more samples. It may be determined, based on performing the operation on the one or more samples, whether to perform the pushdown of the operation.
US09569441B2
In one embodiment, a method determines data stored in a plurality of tables in a first database for archiving. The data is combined from the plurality of tables into a set of objects in a readable format where an object in the set of objects includes terms from the plurality of tables associated with the object. The method then stores the set of objects in the text format in a second database where a search query processor is able to search terms in the set of objects in the readable format. Then, the data stored in the plurality of tables in the first database is deleted in response to the archiving.
US09569433B1
Disclosed are various embodiments for taking measurements associated with the execution of an application on one or more client devices. A measurement policy and/or a transmission policy may be defined by a developer with associated with an application. The measurement policy and/or transmission policy may be used by the one or more client devices in taking measurements, aggregating measurements into measurement collections, and/or transmitting measurements. The measurements may be used in the derivation of statistical information.
US09569414B2
The present invention provides an approach and corresponding framework that separates data from its formatting/view by generating the dynamic JavaScript (data) as a set (e.g., at least one) of JavaScript (data) objects, without any HTML formatting. Then, a set of JavaScript functions can be created that takes the set of JavaScript objects as a parameter, and outputs all or a subset of this data object in a format determined by this JavaScript function. In general, these formatting functions can be static, rather than dynamic, JavaScript. This approach has the advantage of providing a much greater degree of formatting flexibility, without the need for each new format to establish a connection with the back-end system providing the data.
US09569413B2
A document is received that has a plurality of lines with text. This document includes text associated with at least one topic of interest and text not associated with the at least one topic of interest. Thereafter, it is determined, for each line in the document, a length of the line and a number of off-topic indicators with the off-topic indicators characterizing portions of the document as likely being not being associated with the at least one topic of interest. Thereafter, a density for each line can be determined based on the determined line length and the determined number of off-topic indicators. The determined densities for each line are used to identify portions of the documents likely associated with the at least one topic of interest so that data characterizing the identified portions of the document can be provided. Related apparatus, systems, techniques and articles are also described.
US09569410B2
An educational digital publication platform coordinates distribution of multilayered content documents to multiple devices of a user. The platform ingests content and transforms it into a form suitable for web-based publication in the form of a multilayered document while preserving page fidelity. EReading browser applications executing on user devices render layers of the multilayered content into a form readable by end users. The publishing platform authenticates or denies requests to access content on each device and manages distribution of the content to the browser applications executing on authenticated devices, thereby effectively connecting multiple devices of the same user. As the end user interacts with the content, activities are logged by the platform and reported to all the user's connected devices in order to synchronize delivery of content and services.
US09569399B2
Routing data communications packets in a parallel computer that includes compute nodes organized for collective operations. Each compute node including an operating system kernel and a system-level messaging module that is a module of automated computing machinery that exposes a messaging interface to applications. Each compute node including a routing table that specifies, for each of a multiplicity of route identifiers, a data communications path through the compute node. Including to carry out the steps of: receiving in a compute node a data communications packet that includes a route identifier value; retrieving from the routing table a specification of a data communications path through the compute node; and routing, by the compute node, the data communications packet according to the data communications path identified by the compute node's routing table entry for the data communications packet's route identifier value.
US09569398B2
Routing data communications packets in a parallel computer that includes compute nodes organized for collective operations. Each compute node including an operating system kernel and a system-level messaging module that is a module of automated computing machinery that exposes a messaging interface to applications. Each compute node including a routing table that specifies, for each of a multiplicity of route identifiers, a data communications path through the compute node. Including to carry out the steps of: receiving in a compute node a data communications packet that includes a route identifier value; retrieving from the routing table a specification of a data communications path through the compute node; and routing, by the compute node, the data communications packet according to the data communications path identified by the compute node's routing table entry for the data communications packet's route identifier value.
US09569394B2
A request to send a first message from a first component to a second component is received at an arbiter. The first component is located in a first time zone and the second component is located in a second time zone. The arbiter determines that the second component is located in the second time zone. It is determined that the second time zone can be communicated with via one or more communications channels in a first direction. It is determined whether bandwidth is available on the one or more communications channels in the first direction. If bandwidth is available on the one or more communications channels in the first direction, a data path between the first component and the one or more communications channels in the first direction is created and the request is granted. Otherwise, the grant of the request is delayed.
US09569391B2
Processing of out-of-order data transfers is facilitated in computing environments that enable data to be directly transferred between a host bus adapter (or other adapter) and a system without first staging the data in hardware disposed between the host bus adapter and the system. An address to be used in the data transfer is determined, in real-time, by efficiently locating an entry in an address data structure that includes the address to be used in the data transfer.
US09569372B2
A method and system of communicating data to or from a remote computer. The remote computer is accessed by a CPU as though it were a local IDE controller attached to a local IDE device. A peripheral device distinct from the CPU provides a set of virtual IDE device registers and an IDE controller to the central processing unit. The peripheral device receives data written to the set of virtual IDE device registers, and transmits the data into a network, addressed for reception by the remote computer. The remote computer receives the data, interprets it, and performs operations upon a mirror set of device data. The remote computer then responds, and transmits its response across the network to the peripheral device. The peripheral device communicates the response to the CPU in a fashion identical to an physical IDE controller attached to a physical IDE device.
US09569367B1
Exemplary methods for improving cache utilization include in response to receiving a request to store data, storing the data in one of a plurality of cache slots of a cache. In one embodiment, the methods further include after storing the data, setting a status of the cache slot as write pending to indicate that the cache slot contains data which needs to be written to a corresponding destination storage device. The methods include determining an eviction type of the cached data based on whether the destination storage device is a local storage device or a remote storage device. In one embodiment, after copying data from the cache slot to the corresponding destination storage device, marking the cache slot with the determined eviction type. In response to receiving another request to store data, evicting at least one of the cache slots based on the eviction type.
US09569363B2
A microprocessor includes a translation lookaside buffer and a first request to load into the microprocessor a page table entry in response to a miss of a virtual address in the translation lookaside buffer. The requested page table entry is included in a page table. The page table encompasses a plurality of cache lines including a first cache line that includes the requested page table entry. The microprocessor also includes hardware logic that makes a determination whether a second cache line physically sequential to the first cache line is outside the page table, and a second request to prefetch the second cache line into the microprocessor. The second request is selectively generated based at least on the determination made by the hardware logic.
US09569362B2
An input/output bridge controls access to a memory by a number of devices. The bridge enforces ordering of access requests according to a register storing an order configuration, which can be programmed to accommodate a given application. When suspending an access request as a result of enforcing an order configuration, the bridge may also cause a prefetch at the memory for the suspended access request. Subsequently, following the completion of a previous access request meeting the order configuration, the suspended access request is released. Due to the prefetch, an access operation can be completed with minimal delay.
US09569344B2
An example of the invention is a test support system for supporting testing of a function of a program that works depending on a position of a mobile object in map information. A storage device holds event generation requirements information defining requirements for generation of an event in the program. The requirements specify a position designated in the map information and requirements on movement of the mobile object with respect to the designated position. A processor creates a plurality of test cases to be referred to in creating test data to be input to the program for checking whether the event is generated in accordance with the requirements with reference to the map information and the requirements. Each of the plurality of test cases specifies the designated position in the map information and movement of the mobile object with respect to the designated position.
US09569341B1
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for assigning levels of priority to selected source code functions. One of the methods includes for each selected function, a respective associated first set of functions reachable from the selected function by at most N steps, and a respective associated second set of functions that are each reachable from the selected function by more than N steps and less than M steps are computed. A first partition having all selected functions whose respective associated first set of functions has at least one of the subject functions is computed. A second partition having selected functions not in the first partition and whose respective associated second set of functions has at least one of the subject functions is computed. Selected functions belonging to the first partition are assigned a higher priority than selected functions belonging to the second partition.
US09569338B1
Techniques relate to fingerprint-initiated trace extraction. A determination is made of whether a fingerprint is present in software that is currently executing on a processor of a computer system. The fingerprint comprises a representation of a sequence of behavior that occurs in the processor while the software is executing. In response to determining that the fingerprint is not present in the software currently executing on the processor, monitoring continues for the software executing on the processor to determine whether the fingerprint is present. In response to determining that the fingerprint is present in the software executing on the processor, a trace is triggered of a code segment of the software corresponding to when the fingerprint is recognized. The trace is for a record of instructions of the code segment of the software.
US09569334B2
Methods, apparatus, and systems for traversing a representation of an application source code, such as an abstract syntax tree (AST), are disclosed. Steps for traversing the AST include specifying a plurality of runtime binding rules which are associated with one or more locations within the AST, beginning to traverse the AST, monitoring a history of the traverse, continuing to traverse the AST based on the history of the traverse, and updating the history of the traverse. Continuing to traverse the AST may include identifying a plurality of concrete implementations of a method invocation and traversing less than all of the concrete implementations based at least in part on the runtime binding rules, the concrete implementations being traversed being selected based on the history of the traverse.
US09569333B1
A method and system for processing recorded communications over a network provides a communication via a network to a recording server adapted for hosting a recordable meeting. The recording server includes a processor with a memory and communicates with the network and an identification code is provided for the recordable meeting along with text related to the communication, which is stored in data storage of the recording server. At least one pointer can be inserted during or after the meeting is recorded, forming a recorded meeting with at least one pointer mapped to the text of the recorded meeting. The recorded meeting with at least one pointer is then saved into the data storage that can be accessed by an interested user.
US09569332B2
A method is provided for detecting irregularities of one or more application programmer interface (API) entities. The method includes receiving a request for data of one or more API entities. The method further includes monitoring said data from at least one server and detecting irregularities in the data. The method also includes displaying information pertaining to the irregularities to a user.
US09569328B2
Applications and their application components run on a cloud platform and an underlying cloud runtime infrastructure. The cloud platform provides a service that exposes an interface to remotely change log levels of logger objects defined in application components. The application logs are generated and stored for the application components on the cloud runtime infrastructure of the cloud platform. Log levels affect the content stored in the application logs. The exposed interface is instantiated to process remote requests for managing application logs and log levels for a specified application component. The application component is deployed on the cloud platform. The requested change in the log levels is performed based on the implementation of the interface. The change in the log levels is performed in the configuration data on the cloud runtime infrastructure provided by the cloud platform.
US09569327B2
An alert processing system and method are adapted for processing device alerts. The system includes a routing device in communication with a printer. The routing device receives at least one alert description in a source language transmitted from the printer. The routing device identifies a set of words derived from the alert description related to a condition of the associated device. The routing device compares the set of words, in a target language, to a categorization model and, based on the comparison, categorizes the set of words into to one of a predetermined set of alert categories.
US09569326B2
Efficiently identifying transactions processed by a software application, such as a server application is disclosed. In one embodiment, transactions are identified by applying a set of rules to communications between a client and server to determine whether certain patterns are in the communications. For example, the rules may look for some combination of parameters in the transactions. As a particular example, the rules may be used to look for parameters in HTTP requests. The rules are organized in a way that allows efficient processing. For example, the rules may be organized based on the frequency with which the parameters are expected to occur in the transactions and the frequency with which each transaction is expected to occur. The rules may be updated if the expected frequencies deviate from actual frequencies, such that the rules can be organized for more efficient processing.
US09569325B2
A method and a system for automated test and result comparison, suitable for a client computer to control a management server to test sensors in a server to be tested, are provided. In the method, an operating interface of a management program of the management server is logged in through a network, and operating actions of a user testing the sensors by using the operating interface are simulated to generate keyboard and mouse control instructions corresponding to the operating actions by using a keyboard-and-mouse automation program. The keyboard and mouse control instructions are executed to operate the operating interface, so as to control the management program to test the sensors. The test parameters obtained by the management program testing the sensors are captured, and compared with predetermined parameters in a database to obtain a test result. Finally, the test result is stored as a test file.
US09569324B2
An information handling system includes a communication device and a service processor. The communication device includes first terminal, and a second terminal to communicate with a network storage array. The service processor includes a first terminal to receive configuration settings for the communication device, and a second terminal to provide the configuration settings to the communication device. The service processor configures the communication device based on the configuration settings during a first boot sequence of the information handling system. A power-on self test of a basic input/output system of the information handling system is stalled while the service processor configures the communication device based on the configuration settings, and the information handling system is booted from a workload on a storage array identified in the configuration settings without using a second boot sequence of the information handling system.
US09569315B2
Techniques disclosed herein enable efficient creation of models that represent connection topology of virtual machine (VM) management servers and site recovery manager (SRM) servers configured to provide VM recovery services across multiple locations. In operation, an SRM topology unit initializes a model to represent a VM management server. The SRM topology unit expands the model to represent a first SRM server that is logically connected to the VM management server and supports VM recovery at a first location. The SRM topology unit further expands the model to reflect a pairing relationship between the first SRM server and a second VM management server that supports VMs at a second location. Creating an easily-comprehended model in this hierarchical and automated fashion improves on conventional techniques where holistically evaluating the connection topology is predominantly a tedious and error-prone manual process.
US09569306B1
A data storage system includes a controller and a non-volatile memory array having a plurality of blocks each including a plurality of physical pages. The controller maintains a logical-to-physical translation (LPT) data structure that maps logical addresses to physical addresses and implements a first data protection scheme that stripes write data over the plurality of physical blocks. In response to a read request requesting data from a target page stripe, the controller detecting errors in multiple physical pages of the target page stripe. In responsive to detecting errors in multiple physical pages of the target page stripe, the controller scans the LPT data structure to identify a set of logical addresses mapped to the target page stripe and triggers recovery of the target page stripe by a higher level controller that implements a second data protection scheme, wherein triggering recovery includes transmitting the set of logical addresses to the higher level controller.
US09569302B1
Decoding using miscorrection detection is disclosed. A measure indicative of the number of proposed corrections included in a set of proposed corrections corresponding to one or more of a plurality of read values is received. The plurality of read values corresponds to a codeword. It is determined whether the number of proposed corrections is a permitted number of corrections.
US09569298B2
A hierarchical multi-stage model of asset failure risk for complex heterogeneously distributed physical assets is built. The hierarchical multi-stage model considers heterogeneity of failure patterns for the assets. At least one data stream is analyzed to determine whether the hierarchical multi-stage model needs to be updated due to a change in the failure patterns. If the analysis indicates that the hierarchical multi-stage model needs to be updated, the hierarchical multi-stage model is dynamically updated to obtain an updated hierarchical multi-stage model.
US09569292B2
A “Remotable Contract Implementation”, as described herein, provides various techniques for implementing static type checking of remoted contracts across iframes using scripts such as TypeScript, JavaScript, AJAX, etc., thereby enabling structured data and rich patterns of control flow across iframe boundaries. The Remotable Contract Implementation enables the static type-checking over the limited browser postMessage channel of communication across iframes, by generating statically type-checked proxies at runtime based on dynamic reflection, and allowing for full fidelity of JavaScript control flow interactions (e.g. methods, events, asynchronous communications, etc.) over that channel. Further, in various embodiments, the Remotable Contract Implementation provides various methods that can be used to produce useful application context for otherwise isolated applications by providing access to particular browser resources or information that would otherwise be unavailable over the postMessage communication channel using conventional scripting techniques.
US09569288B2
API associations among a plurality of service application programming interfaces may be identified by analyzing service API call logs, which contain data associated with invocation of the plurality of application programming interfaces by a plurality of applications, wherein sets of APIs that are determined to be called together are identified. For a set of service APIs, a plurality of applications that invoke the APIs in the set is identified. A sequence of API calls by an application in the plurality of applications is identified, wherein multiples sequences of APIs are identified, one sequence of API calls identified respectively for one application in the plurality of applications. An application pattern is determined based on the multiple sequences of service APIs.
US09569267B2
The present disclosure is directed to hardware-based inter-device resource sharing. For example, a remote orchestrator (RO) may provide instructions to cause a device to make at least one hardware resource available to other devices. An RO module in the device may interact with the RO and may configure a configuration module in the device based on instructions received from the RO. The configuration module may set a device configuration when the device transitions from a power off state to a power on state. The device may also comprise a processing module to process data based on the device configuration, interface technology (IT) and at least one hardware resource. The interface technology may allow the processing module and the at least one hardware resource to interact. The RO module may configure the IT to allow the at least one hardware resource to operate locally or remotely based on the instructions.
US09569256B2
A method may include associating, with a timer-B, a second application in a terminal device; setting the terminal device in a standby mode; and executing the second application when a processor in the terminal device wakes up after the timer-B measures a second amount of elapsed time. The timer-B may not initiate wake-up of the processor. The method may further include determining whether the second application is associated with the timer-B or a timer-A when the terminal device receives a command of setting the terminal device in the standby mode; and when the second application is determined as being associated with the timer-A, unassociating the second application with the timer-A. The timer-A may initiate wake-up of the processor when the timer-A measures another second amount of elapsed time while the terminal device is the standby mode. A timer associated with a first application may initiate wakeup of the processor.
US09569247B2
A method performed by a physical computing system includes, with a hypervisor, determining that a multilevel guest page table includes an upper directory that maps a set of contiguous entries to privileged pages, with the hypervisor, determining that, within the multilevel page table, only the set of contiguous entries map to the privileged pages, with the hypervisor, receiving a request from the guest to execute a virtual machine function, receiving a pointer as a parameter for the virtual machine function, and in response to determining that the pointer references a memory address that is within a range associated with the set of contiguous entries, aborting the virtual machine function.
US09569241B2
An example system and method of sharing a device assigned to a plurality of virtual machines includes identifying a first virtual machine in which a device is active. When a condition is satisfied, control of the device is transferred from the first virtual machine to a second virtual machine. Transferring control of the device includes sending a first communication to cause the first virtual machine to relinquish control of the device based on an indication that power will be removed from the device and further to cause the virtual machine to save first state information maintained by the first virtual machine to a first memory. The first state information is associated with the device. Transferring control of the device also includes saving second state information maintained by a host machine to a second memory. The second state information is associated with the first virtual machine and device.
US09569238B2
Techniques and systems for modifying a virtual machine functionality. Archive files each including at least a class files are received. The archive files are stored within the virtual machine. The virtual machine runs on a host system and neither the virtual machine nor the host system are restarted in response to the receiving or storing of the archive files. Files of the host system are scanned to find class files that are not included in a class path for the virtual machine. The class files are copied to a class path for the virtual machine. Neither the virtual machine nor the host system are restarted in response to the copying of the class files. The classes corresponding to the class files are registered in the virtual machine in response to the copying of the class files to the class path. Neither the virtual machine nor the host system are restarted in response to the registration of the classes.
US09569233B2
Embodiments are directed towards employing a traffic management system (TMS) that is enabled to deploy component virtual machines (CVM) to the cloud to perform tasks of the TMS. In some embodiments, a TMS may be employed with one or more CVMs. In at least one embodiment, the TMS may maintain an image of each CVM. Each CVM may be configured to perform one or more tasks, to operate in specific cloud infrastructures, or the like. The TMS may deploy one or more CVMs locally and/or to one or more public and/or private clouds. In some embodiments, deployment of the CVMs may be based on a type of task to be performed, anticipated resource utilization, customer policies, or the like. The deployment of the CVMs may be dynamically updated based on monitored usage patterns, task completions, customer policies, or the like.
US09569232B1
Approaches are described for collecting and/or utilizing network traffic information, such as network flow data, within a virtualized computing environment. The network traffic information can be collected on one or more host computing devices that host virtual machines. The collected network traffic information can include virtualized computing environment specific information, such as a user account identifier (ID), virtual machine identifier (ID), session termination information and the like. The collected network traffic information can also be presented to the user of the virtualized computing environment.