US10164250B2
There is provided a lithium-iron-manganese-based composite oxide capable of providing a lithium-ion secondary battery which has a high capacity retention rate in charge/discharge cycles and in which the generation of a gas caused by charge/discharge cycles is reduced. A lithium-iron-manganese-based composite oxide having a layered rock-salt structure, wherein at least a part of the surface of a lithium-iron-manganese-based composite oxide represented by the following formula (1) is coated with an inorganic material: LixM1(y-p)MnpM2(z-p)FeqO(2-δ) (1) (wherein 1.05≤x≤1.32, 0.33≤y≤0.63, 0.06≤z≤0.50, 0
US10164246B2
The present disclosure relates to a sulfur-carbon composite and a preparing method thereof, and more particularly, to a sulfur-carbon composite having an aggregated structure by performing a pressure heat treatment on a mixture of a carbonaceous conductive material and a sulfur-containing amorphous carbon material and carbonizing the same, and a preparing method thereof.
US10164233B2
To provide a lithium ion secondary battery that is less likely affected by vibration, shock, or the like.A stacked lithium ion secondary battery is characterized in that separators, which are stacked with positive and negative electrodes, are a flat bag or flat tube with at least one side of an outer periphery thereof intermittently heat-sealed; the heat-sealed side is provided with concave and convex portions made up of straight lines or curves or a combination of straight lines and curves; the outer periphery of the separator made with the concave and convex portions is positioned outside the outer periphery of the negative electrode along with the concave and convex portions; and the outer periphery of the negative electrode is positioned outside the outer periphery of the positive electrode housed in the bag-shape or tubular separator.
US10164231B2
This invention, in some variations, provides a separator for a lithium-sulfur battery, comprising a porous substrate that is permeable to lithium ions; and a lithium-ion-conducting metal oxide layer on the substrate, wherein the metal oxide layer includes deposits of sulfur that are intentionally introduced prior to battery operation. The deposits of sulfur may be derived from treatment of the metal oxide layer with one or more sulfur-containing precursors (e.g., lithium polysulfides) prior to operation of the lithium-sulfur battery. Other variations provide a method of charging a lithium-sulfur battery that includes the disclosed separator, the charging being accomplished by continuously applying a substantially constant voltage to the lithium-sulfur battery until the battery charging current is at or below a selected current.
US10164222B2
A battery module is provided. The battery module includes a battery module comprising a plurality of battery units comprising a pair of terminals respectively; and a connector comprising insertion portions, wherein the pair of terminals are inserted into the insertion portions and the plurality of terminals are electrically connected to each other.
US10164216B2
The present application discloses an organic light emitting diode base substrate including a support substrate and a light outcoupling layer on the support substrate for enhancing light outcoupling efficiency of an organic light emitting display substrate, the light outcoupling layer having a corrugated surface on a side of the light outcoupling layer distal to the support substrate. The light outcoupling layer including a polymer material having a gradient distribution in a direction from the corrugated surface to the support substrate.
US10164214B2
The disclosure provides a display panel and a method for manufacturing the same. The display panel includes: an underlying substrate; thin film transistors, a light emission layer, a first inorganic moisture-blocking layer successively arranged on the underlying substrate; an organic buffer layer arranged on the first inorganic moisture-blocking layer, the organic buffer layer comprises: droplet micro-structures for decentralizing a stress on the organic buffer layer; a second inorganic moisture-blocking layer arranged on the organic buffer layer; and a blocking layer, and a glass cover plate successively arranged on the second inorganic moisture-blocking layer.
US10164205B2
A device including an emissive material comprising quantum dots is disclosed. In one embodiment, the device includes a first electrode and a second electrode, a layer comprising quantum dots disposed between the first electrode and the second electrodes, and a first interfacial layer disposed at the interface between a surface of the layer comprising quantum dots and a first layer in the device. In certain embodiments, a second interfacial layer is optionally further disposed on the surface of the layer comprising quantum dots opposite to the first interfacial layer. In certain embodiments, a device comprises a light-emitting device. Other light emitting devices and methods are disclosed.
US10164202B2
An organic electroluminescence device according to one aspect of the present invention includes: a substrate; a thin film transistor provided above the substrate; a flattening layer provided above the thin film transistor and including a contact hole which is open on a side opposite to the substrate; a reflecting layer provided along at least a surface of the contact hole; a light-transmitting filling layer configured to fill an inside of the contact hole with the reflecting layer therebetween; and an organic EL element formed above the flattening layer and a contact hole top.
US10164189B2
The present invention relates to a novel polymer comprising a thiadiazol group, the production of such a polymer, its use in organic electronic devices as well as such organic electronic devices.
US10164188B2
A polymer-hybrid electro-optic device is fabricated by providing a semiconductor substrate, depositing a metal electrode layer on the semiconductor substrate, depositing a dielectric barrier core layer within a gap of the metal electrode layer, patterning a polymer layer to cover the dielectric barrier core layer and partially covering the metal electrode layer, infiltrating the polymer layer with an inorganic component to form a hybrid oxide-polymer layer, and removing excess inorganic component from the semiconductor substrate and metal electrode layer.
US10164185B2
In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by turning on a PMOS transistor having a drain terminal coupled to a lower electrode of an RRAM device. A first voltage is provided to a source terminal of the PMOS transistor, and a second voltage is provided to a bulk terminal of the PMOS transistor. The second voltage is larger than the first voltage. A third voltage is provided to an upper electrode of the RRAM device. The third voltage is larger than the first voltage.
US10164183B2
A semiconductor device includes at least one bottom electrode, a resistive layer, and a top electrode. The bottom electrode has two opposite sidewalls. The resistive layer is disposed on the bottom electrode, extends past at least one of the two opposite sidewalls of the at least one bottom electrode, and has a variable resistance. The resistive layer is disposed on the bottom electrode and extends past at least one of the two opposite sidewalls of the at least one bottom electrode.
US10164181B2
A memory device includes a bottom electrode, a resistance switching element, a top electrode, a spacer and a conductive feature. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching electrode. The spacer abuts the resistance switching element. The conductive feature is over the top electrode. The spacer is at least partially between the conductive feature and the top electrode.
US10164176B2
A method of manufacturing one or more interconnects to a magnetoresistive structure, the method comprising depositing a first conductive material (i) in a via which is formed through a first surface of a first dielectric layer and (ii) directly on the first surface of the first dielectric layer. The method further includes etching the first conductive material wherein, after etching the first conductive material, a portion of the first conductive material remains (i) in the via and (ii) directly on the first surface of the first dielectric layer. The method also includes partially filling the via by depositing a second conductive material (i) in the via and (ii) directly on the first conductive material remaining in the via, depositing a first electrode material (i) in the via and (ii) directly on the second conductive material which is in the via, and forming a magnetoresistive structure over the first electrode material.
US10164173B2
Magnetic random access memory (MRAM) devices, and methods of manufacturing the same, include at least one first magnetic material pattern on a substrate, at least one second magnetic material pattern on the at least one first magnetic material pattern, and at least one tunnel barrier layer pattern between the at least one first magnetic material pattern and the at least one second magnetic material pattern. A width of a top surface of the at least one first magnetic material pattern may be less than a width of a bottom surface of the at least one second magnetic material pattern.
US10164160B2
A light emitting structure includes a packaged back-emitting light emitting device mounted on a reflective substrate. The properties of the reflective surface may be controlled to provide a desired luminance pattern. In this manner, the creation of a light emitting structure that provides a desired luminance pattern may be independent of the provider of the packaged light emitting device.
US10164146B2
A light emitting device includes a p-side heterostructure having a short period superlattice (SPSL) formed of alternating layers of AlxhighGa1-xhighN doped with a p-type dopant and AlxlowGa1-xlowN doped with the p-type dopant, where xlow≤xhigh≤0.9. Each layer of the SPSL has a thickness of less than or equal to about six bi-layers of AlGaN.
US10164145B2
A method for manufacturing a light emitting unit is provided. A semiconductor structure including a plurality of light emitting dice separated from each other is provided. A molding compound is formed to encapsulate the light emitting dice. Each of the light emitting dice includes a light emitting element, a first electrode and a second electrode. A patterned metal layer is formed on the first electrodes and the second electrodes of the light emitting dice. A substrate is provided, where the molding compound is located between the substrate and the light emitting elements of the light emitting dice. A cutting process is performed to cut the semiconductor structure, the patterned metal layer, the molding compound and the substrate so as to define a light emitting unit with a series connection loop, a parallel connection loop or a series-parallel connection loop.
US10164138B2
Photovoltaic module with a negative terminal (5) and a positive terminal (6), and a parallel connection (3, 4) of m sub-modules (2) connected to the negative and the positive terminal (5, 6) of the photovoltaic module (1). Each of the m sub-modules (2) has a string of n series-connected back-contact cells (9), wherein the n cells (9) of each sub-module (2) are arranged in an array. The parallel connection (3, 4) and connections (8) for each string of n series-connected back contact cells (9) are provided in a back conductive sheet, and the back conductive sheet comprises designated areas (7) for the parallel connection (3, 4), corresponding to edge parts of each corresponding sub-module (2).
US10164134B2
An optoelectronic semiconductor chip is disclosed. In an embodiment the chip includes an active zone with a multi-quantum-well structure, wherein the multi-quantum-well structure comprises multiple quantum-well layers and multiple barrier layers, which are arranged sequentially in an alternating manner along a growth direction, wherein the multi-quantum-well structure has at least one emission region and multiple transport regions which are arranged sequentially in an alternating manner in a direction perpendicular to the growth direction, wherein at least one of the quantum-well layers and the barrier layers are thinner in the transport regions than in the emission regions, and wherein the quantum-well layers in the transport regions and in the emission regions are oriented perpendicularly to the growth direction with exception of a junction region between adjacent transport regions and emission regions.
US10164127B2
One embodiment of the present invention provides a solar module. The solar module includes a front-side cover, a back-side cover, and a plurality of solar cells situated between the front- and back-side covers. A respective solar cell includes a multi-layer semiconductor structure, a front-side electrode situated above the multi-layer semiconductor structure, and a back-side electrode situated below the multi-layer semiconductor structure. Each of the front-side and the back-side electrodes comprises a metal grid. A respective metal grid comprises a plurality of finger lines and a single busbar coupled to the finger lines. The single busbar is configured to collect current from the finger lines.
US10164126B2
A semiconductor power rectifier with increased surge current capability is described. A semiconductor layer includes a drift layer having a first conductivity type, at least one pilot region having a second conductivity type different from the first conductivity type, a plurality of stripe-shaped emitter regions having the second conductivity type, and a transition region having the second conductivity type, wherein the at least one pilot region has in any lateral direction parallel to the first main side a width of at least 200 μm and is formed adjacent to the first main side to form a first p-n junction with the drift layer, each emitter region is formed adjacent to the first main side form a second p-n junction with the drift layer, and the transition region is formed adjacent to the first main side to form a third p-n junction with the drift layer.
US10164125B2
A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.
US10164122B2
A method includes depositing a first transition metal film having a first transition metal on a substrate and performing a first sulfurization process to the first transition metal film, thereby forming a first transition metal sulfide film. The method further includes depositing a second transition metal film having a second transition metal on the first transition metal sulfide film and performing a second sulfurization process to the second transition metal film, thereby forming a second transition metal sulfide film. The first and the second transition metals are different. The method further includes forming a gate stack, and source and drain features over the second transition metal sulfide film. The gate stack is interposed between the source and drain features. The gate stack, source and drain features, the first transition metal sulfide film and the second transition metal sulfide film are configured to function as a hetero-structure transistor.
US10164121B2
A semiconductor device including: a substrate; a first active layer on the substrate and including a first channel between a source and a drain; a second active layer stacked on the first active layer, the second active layer including a second channel between the source and the drain; a first gate corresponding to the first channel; and a second gate electrically separated from the first gate and corresponding to the second channel.
US10164120B2
A transistor including a semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator is manufactured by forming a hard mask layer including a fourth conductor over the second insulator, a third insulator over the fourth conductor, forming an opening portion in the second insulator with the hard mask layer as the mask, eliminating the hard mask layer by forming the opening portion, and forming the first insulator and the first conductor in the opening portion.
US10164112B2
A semiconductor device includes a substrate; at least one source/drain feature at least partially disposed in the substrate; an isolation structure disposed on the substrate and includes a first portion; a gate structure disposed on the first portion of the isolation structure and adjacent to the source/drain feature; and at least one gate spacer disposed on a sidewall of the gate structure, in which a top surface of the first portion of the isolation structure is in contact with the gate structure and is higher than a bottommost surface of the gate spacer.
US10164111B2
A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.
US10164098B2
A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.
US10164079B2
A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body having a front side, a backside, a first load terminal, and a drift region. A first cell is arranged at the front side. Further, the power semiconductor device comprises: a first backside emitter region included in the semiconductor body, the first backside emitter region being electrically connected with the second load terminal and having dopants of the second conductivity type, wherein the first backside emitter region and the first cell have a first common lateral extension range; and a second backside emitter region included in the semiconductor body, the second backside emitter region being electrically connected with the second load terminal and having dopants of the first conductivity type, wherein the second backside emitter region and the second cell have a second common lateral extension range.
US10164074B2
A semiconductor device includes a semiconductor substrate, a gate dielectric layer, a gate electrode and source and drain regions. The gate dielectric layer extends into a first trench in the semiconductor substrate. The gate electrode is over the gate dielectric layer and is at least partially embedded in the first trench in the semiconductor substrate. The source and drain regions are in the semiconductor substrate and proximate the first trench in the semiconductor substrate.
US10164064B2
An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.
US10164056B2
Provided is a method for forming a semiconductor structure. In one or more embodiments of the invention, the method includes forming a semiconductor fin on a substrate and decreasing a width of the semiconductor fin. The method further includes forming a spacer layer on a surface of the substrate and forming a high dielectric constant layer on exposed surfaces of the semiconductor fin and the spacer layer. The method also includes forming a work function metal layer on the high dielectric constant layer. The method also includes removing portions of the work function metal layer and the high dielectric constant layer to expose portions of the spacer layer. A thickness of the remaining work function metal layer on sidewalls of the semiconductor fin is uniform.
US10164039B2
A semiconductor device having metal gate includes a substrate, a metal gate formed on the substrate, a pair of spacers formed on sidewalls of the metal gate, a contact etch stop layer (CESL) covering the spacers, an insulating cap layer formed on the metal gate, the spacers and the CESL, and an ILD layer surrounding the metal gate, the spacers, the CESL and the insulating cap layer. The metal gate, the spacers and the CESL include a first width, and the insulating cap layer includes a second width. The second width is larger than the first width. And a bottom of the insulating cap layer concurrently contacts the metal gate, the spacers, the CESL, and the ILD layer.
US10164034B2
A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact, a separator, a plug contacting the source/drain contact and a wiring contacting the plug. The fin structure protrudes from an isolation insulating layer and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact is disposed on the first source/drain region. The separator is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact are in contact with a same face of the separator.
US10164033B2
A semiconductor device includes a fin having a first semiconductor material. The fin includes a source/drain (S/D) region and a channel region. The S/D region provides a top surface and two sidewall surfaces. A width of the S/D region is smaller than a width of the channel region. The semiconductor device further includes a semiconductor film over the S/D region and having a doped second semiconductor material that is different from the first semiconductor material. The semiconductor film provides a top surface and two sidewall surfaces over the top and two sidewall surfaces of the S/D region respectively. The semiconductor device further includes a metal contact over the top and two sidewall surfaces of the semiconductor film and operable to electrically communicate with the S/D region.
US10164029B2
A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a conductive plug. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure while leaving a gap between the conductive plug and the spacer.
US10164025B2
A semiconductor device comprises a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region. Further it comprises a plurality of needle-shaped cell trenches within the cell region reaching from a surface of the semiconductor substrate structure into the substrate structure and an edge termination trench within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure.
US10164023B2
A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.
US10164018B1
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphene barrier layers can be selected by varying the thickness of the amorphous carbon layer.
US10164016B2
The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration
US10164013B2
Formation methods of a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate and forming a source/drain structure adjacent to the gate stack. The method also includes forming a cap element over the source/drain structure. The cap element has a top surface and a side surface, and a width ratio of the top surface to the side surface of the cap element is in a range from about 0.125 to about 1.
US10164005B2
The present disclosure provides a semiconductor structure which comprises a semiconductive substrate and a doped region in the semiconductive substrate. The doped region has a conductivity type opposite to the semiconductive substrate. The semiconductor structure also includes a capacitor in the doped region where the capacitor comprises a plurality of electrodes and the plurality of electrodes are insulated with one another. The semiconductor structure further includes a plug in the capacitor and surrounded by the plurality of electrodes.
US10163999B2
A display device includes a substrate including a display area and a peripheral area disposed around the display area. The peripheral area includes a bending region and a contact region adjacent to the bending region. A first connection line includes a first portion disposed in the contact region, and a second portion disposed in both the bending region and the contact region, and including a first layer and a second layer. At least part of the second layer of the second portion overlaps the first layer of the second portion. In the contact region, the first layer of the second portion is electrically connected to the first portion, and the second layer of the second portion is electrically connected to the first layer of the second portion.
US10163997B2
The present invention discloses an OLED array substrate and a manufacturing method thereof, a display apparatus. The OLED array substrate includes a TFT and an OLED. The method includes: forming an oxide semiconductor layer by a film forming process, and performing one patterning process on the oxide semiconductor layer to form an active layer of the TFT and a first electrode of the OLED; sequentially forming a first insulating layer and a second insulating layer on the active layer and the first electrode of the OLED, the first insulating layer being a lyophilic layer, and the second insulating layer being a lyophobic layer; forming an accommodation cavity exposing the first electrode by performing a patterning process on the first and second insulating layers; and injecting, into the accommodation cavity, and drying a solution containing an organic light emitting material to form an organic light emitting material layer.
US10163989B2
A display device that has an excellent visibility even under strong light is provided. In the display device, a first display element that reflects visible light and a second display element that emits visible light are between a first substrate and a second substrate. The display device can display an image with high visibility by operating the first display element under strong light and operating the second display element under weak light. Furthermore, a first surface of the second substrate is provided with a touch sensor, and a second surface opposite to the first surface is provided with an anti-reflection layer. Such a structure can sufficiently reduce reflection of external light on the display surface under strong light, further increasing the visibility.
US10163980B2
A method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure.
US10163975B2
A light emitting apparatus is disclosed. The light emitting apparatus includes a light-transmissive substrate having a top surface and a bottom surface, at least one semiconductor light emitting device disposed on the top surface of the light-transmissive substrate, a reflective part disposed over the semiconductor light emitting device to reflect light from the semiconductor light emitting device toward the light-transmissive substrate, and a first wavelength converter disposed between the light-transmissive substrate and the reflective part.
US10163966B2
Some embodiments of the present disclosure provide a method of manufacturing a back side illuminated (BSI) image sensor. The method includes receiving a semiconductive substrate; forming a photosensitive element at a front side of the semiconductive substrate; forming a transistor coupled to the photosensitive element; forming a recess at a back side of the semiconductive substrate; forming a first dielectric layer lining to a side portion of the recess and over the back side of the semiconductor substrate; covering a conductive material over the first dielectric layer and filling in the recess; forming a conductive column on top of the recess by patterning the conductive material; and forming a second dielectric layer covering the conductive column and the first dielectric layer.
US10163963B2
Image sensors may include multiple vertically stacked photodiodes interconnected using vertical deep trench transfer gates. A first n-epitaxial layer may be formed on a residual substrate; a first p-epitaxial layer may be formed on the first n-epitaxial layer; a second n-epitaxial layer may be formed on the first p-epitaxial layer; a second p-epitaxial layer may be formed on the second n-epitaxial layer; and so on. The n-epitaxial layers may serve as accumulation regions for the different epitaxial photodiodes. A separate color filter array is not needed. The vertical transfer gates may be a deep trench that is filled with doped conductive material, lined with gate dielectric liner, and surrounded by a p-doped region. Image sensors formed in this way may be used to support a rolling shutter configuration or a global shutter configuration and can either be front-side illuminated or backside illuminated.
US10163962B2
The present technology relates to a solid-state imaging apparatus, a manufacturing method therefor, and an electronic apparatus by which fine pixel signals can be suitably generated.A charge accumulation section that is formed on a first semiconductor substrate and accumulates photoelectrically converted charges, a charge-retaining section that is formed on a second semiconductor substrate and retains charges accumulated in the charge accumulation section, and a transfer transistor that is formed on the first semiconductor substrate and the second semiconductor substrate and transfers charges accumulated in the charge accumulation section to the charge-retaining section are provided. A bonding interface between the first semiconductor substrate and the second semiconductor substrate is formed in a channel of the transfer transistor.
US10163961B2
An image sensor may include a pixel array that includes a plurality of pixel blocks arranged in an M×N (where M and N are natural numbers) matrix structure, wherein, among the plurality of pixel blocks, when compared to any one pixel block as a first pixel block, any one pixel block as a second pixel block adjacent to the first pixel block in an M direction or an N direction has a planar shape that is obtained by inverting a planar shape of the first pixel block in the M direction. Each of the plurality of pixel blocks may include a light reception unit including a plurality of unit pixels which generate photocharges in response to incident light and are arranged in an m×n matrix structure to have a shared pixel structure; and a driving circuit suitable for outputting an image signal corresponding to the photocharges.
US10163955B2
Disclosed are structures and methods of forming the structures so as to have a photodetector isolated from a substrate by stacked trench isolation regions. In one structure, a first trench isolation region is in and at the top surface of a substrate and a second trench isolation region is in the substrate below the first. A photodetector is on the substrate aligned above the first and second trench isolation regions. In another structure, a semiconductor layer is on an insulator layer and laterally surrounded by a first trench isolation region. A second trench isolation region is in and at the top surface of a substrate below the insulator layer and first trench isolation region. A photodetector is on the semiconductor layer and extends laterally onto the first trench isolation region. The stacked trench isolation regions provide sufficient isolation below the photodetector to allow for direct coupling with an off-chip optical fiber.
US10163954B2
A trenched device wafer includes a device substrate layer having a top surface; a plurality of devices in the device substrate layer, and a trench in the top surface. The trench extends into the device substrate layer, and is located between a pair of adjacent devices of the plurality of devices. A method for forming a device die from a device wafer includes forming a trench in a top surface of the device wafer between two adjacent devices of the device wafer. The trench has a bottom surface located (a) at a first depth beneath the top surface and (b) at a first height above a wafer bottom surface. The method also includes, after forming the trench, decreasing a thickness of the device wafer, between the two adjacent devices, to a thickness less than the first height.
US10163942B2
According to example embodiments, an image display panel assembly includes a flexible printed circuit (FPC), an image display panel, at least one gate driver integrated circuit (IC) package, and at least one source driver IC package. The FPC is configured to receive gate and source driving signals. The image display panel is electrically connected to the FPC, and includes a gate driving signal transfer pattern along a first edge of the image display panel, a source driving signal transfer pattern along a second edge adjacent to the first end, and a plurality of pixels. The at least one gate driver integrated circuit (IC) package is configured to receive the gate driving signal through the gate driving signal transfer pattern and configured to provide the gate driving signal to gate lines of the plurality of pixels. The at least one source driver IC package is configured to receive the source driving signal through the source driving signal transfer pattern and configured to provide the source driving signal to source lines of the plurality of pixels.
US10163935B2
The present invention provides a thin film transistor, an array substrate and a display device. The thin film transistor comprises an active layer, a source electrode and a drain electrode. The active layer comprises a source electrode contact region and a drain electrode contact region, and a semiconductor channel region arranged between the source electrode contact region and the drain electrode contact region. A conductive layer is provided on the semiconductor channel region and is spaced apart from the source electrode and the drain electrode.
US10163915B1
A vertical SRAM cell includes a first (1st) inverter having a 1st pull-up (PU) transistor and a 1st pull-down (PD) transistor. The 1st PU and 1st PD transistors have a bottom source/drain (S/D) region disposed on a substrate and a channel extending upwards from a top surface of the bottom S/D region. A second (2nd) inverter has a 2nd PU transistor and a 2nd PD transistor. The 2nd PU and 2nd PD transistors have a bottom S/D region disposed on the substrate and a channel extending upwards from a top surface of the bottom S/D region. A 1st metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 1st PU and 1st PD transistors. A 2nd metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 2nd PU and 2nd PD transistors.
US10163912B2
A method of forming a semiconductor device includes receiving a substrate with a plurality of gate structures; forming spacers on sidewalls of the gate structures; evaluating a pitch variation to the gate structures; determining an etch recipe according to the pitch variation; performing an etch process to source/drain regions associated with the gate structures using the etch recipe, thereby forming source/drain recesses with respective depths; and performing an epitaxy growth to form source/drain features in the source/drain recesses using a semiconductor material.
US10163906B2
Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region; a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region; a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region; and a gate located over the first, second, and third channel regions. The first and second diffusion regions are located on a first side of the gate. The third and fourth diffusion regions are located on a second side of the gate opposite from the first side.
US10163901B1
Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in flash and logic regions; recessing an oxide exposing an upper portion of the fins; forming an oxide liner over the upper portion in the flash region; forming a polysilicon gate over and perpendicular to the fins in both regions; removing the gate from the logic region and patterning the gate in the flash region forming a separate gate over each fin; forming an ONO layer over the gates in the flash region; forming a second polysilicon gate over and perpendicular to the fins in both regions; planarizing the second polysilicon gate exposing a portion of the ONO layer over the gates in the flash region; forming and patterning a hardmask, exposing STI regions between the flash and logic regions; and forming an ILD over the STI regions.
US10163899B2
The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.
US10163887B2
A semiconductor device includes a first gate stack over an insulator, a second gate stack over an active region, a first dielectric layer over the first and second gate stacks, a second dielectric layer over the first dielectric layer, and a metal layer over the first and second gate stacks. The first and second dielectric layers include different materials. The metal layer contacts the second gate stack by penetrating at least the first and second dielectric layers and is isolated from the first gate stack by at least the first and second dielectric layers.
US10163886B2
A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping line segment electrically coupled with a pass device of the first memory cell; and a second word line strapping line segment. The second memory cell includes a first word line strapping line segment; and a second word line strapping line segment electrically coupled with a pass device of the second memory cell. The first word line strapping line segment of the first memory cell and the first word line strapping line segment of the second memory cell are connected with each other at a first interconnection layer. The second word line strapping line segment of the first memory cell and the second word line strapping line segment of the second memory cell are connected with each other at the first interconnection layer.
US10163878B2
A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate including a front surface and a back surface; a backside metallization layer formed over the semiconductor substrate, the backside metallization layer being closer to the back surface than to the front surface of the semiconductor substrate, at least a portion of the backside metallization layer forming an inductor structure; and an electrically non-conductive material formed in the semiconductor substrate, the electrically non-conductive material at least partially overlapping the inductor structure from a top view, and the electrically non-conductive material including a top surface, a bottom surface, and sidewalls, the top surface being adjacent to the back surface of the semiconductor substrate. A method for manufacturing a semiconductor structure is also disclosed.
US10163860B2
A semiconductor package structure includes an encapsulant, a first chip, a second chip, a first redistribution layer and a second redistribution layer. The encapsulant has a first surface and a second surface opposite to each other. The first chip is in the encapsulant, wherein the first chip includes a plurality of contact pads exposed from the first surface of the encapsulant. The second chip is in the encapsulant, wherein second chip includes a plurality of contact pads exposed from the second surface of the encapsulant. The first redistribution layer is over the first surface of the encapsulant and electrically connected to the contact pads of the first chip. The second redistribution layer is over the second surface of the encapsulant and electrically connected to the contact pads of the second chip.
US10163859B2
A chip package is provided. The chip package includes a semiconductor chip and a semiconductor die over the semiconductor chip. The chip package also includes a dielectric layer over the semiconductor chip and encapsulating the semiconductor die, and the dielectric layer is substantially made of a semiconductor oxide material. The chip package further includes a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting a conductive pad of the semiconductor chip.
US10163857B2
A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.
US10163854B2
A package structure includes a package, at least one second molding material, and at least one electronic component. The package includes at least one first semiconductor device therein, a first molding material, at least one dielectric layer and at least one redistribution line. The first molding material is at least in contact with at least one sidewall of the first semiconductor device. The dielectric layer is over the first semiconductor device and the first molding material. The redistribution line is present at least partially in the dielectric layer and is electrically connected to the first semiconductor device. The second molding material is present on the package. The electronic component is present on the package and is external to the second molding material.
US10163842B2
A semiconductor structure includes an interconnect structure, at least one first metal pad, at least one second metal pad, at least one first bump, at least one second bump, at least one photosensitive material, and a bonding layer. The first metal pad and the second metal pad are disposed on and electrically connected to the interconnect structure. The first bump is disposed on the first metal pad. The second bump is disposed on the second metal pad. The photosensitive material is disposed on the first bump. The bonding layer is in contact with the photosensitive material and the second bump. The photosensitive material is disposed between the first bump and the bonding layer.
US10163841B2
A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least a metal pillar and a plurality of bumps formed on and electrically coupled to the interconnect structures.
US10163811B2
A semiconductor package structure comprises: a high-voltage depletion type semiconductor transistor comprising a source electrode, a gate electrode and a drain electrode; a low-voltage enhancement type semiconductor transistor comprising a source electrode, a gate electrode and a drain electrode; a shell comprising a cavity for receiving the high-voltage depletion type semiconductor transistor and the low-voltage enhancement type semiconductor transistor, and a high-voltage terminal, a first low-voltage terminal and a second low-voltage terminal; and cascade circuits comprising a supporting sheet having a conductive surface. The source electrode of the high-voltage depletion type transistor and the drain electrode of the low-voltage enhancement type semiconductor transistor are fixed to the conductive surface of the supporting sheet and electrically connected to each other through the conductive surface of the supporting sheet. A side of the supporting sheet away from the conductive surface is fixed to the cavity of the shell.
US10163798B1
An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.
US10163787B2
The semiconductor structure includes a first conductive path including first and second segments. The first segment is in a first conductive layer. The second segment is in a second conductive layer. The first and second segments are electrically connected. The semiconductor structure includes a second conductive path including third and fourth segments. The third segment is in the first conductive layer. The fourth segment is in the second conductive layer. The third and fourth segments are electrically connected. The semiconductor structure includes a third conductive path between the first conductive path and the second conductive path, the third conductive path includes fifth and sixth segments. The fifth segment is in the second conductive layer. The sixth segment is in the first conductive layer. The fifth and sixth segments are electrically connected. An area of the first conductive layer between the first and third segments is free of the sixth segment.
US10163786B2
A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements.
US10163784B2
A semiconductor device and a method for manufacturing the same are disclosed. In the semiconductor device, an upper part of a storage node contact plug is increased in size, and an area of overlap between a storage node formed in a subsequent process and a storage node contact plug is increased, such that resistance of the storage node contact plug is increased and device characteristics are improved. The semiconductor device includes at least one bit line formed over a semiconductor substrate, a first storage node contact plug formed between the bit lines and coupled to an upper part of the semiconductor substrate, and a second storage node contact plug formed over the first storage node contact plug, wherein a width of a lower part of the second storage node contact plug is larger than a width of an upper part thereof.
US10163783B1
An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.
US10163782B2
A fuse structure includes a fusing line including a first portion, a second portion, and a central portion between the first portion and the second portion; and a dummy fuse neighboring the fusing line, the dummy fuse may include: a first air dummy fuse including a plurality of first air gaps extending in a first direction parallel to the fusing line; and a second air dummy fuse including a second air gap extending in a second direction crossing the fusing line.
US10163778B2
A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive feature over the semiconductor substrate. The semiconductor device structure also includes a dielectric layer over the conductive feature and the semiconductor substrate. The semiconductor device structure further includes a conductive via surrounded by the dielectric layer and electrically connected to the conductive feature. The conductive via has a lower end and an upper end larger than the lower end, and the conductive via has a side surface curved inward.
US10163777B2
Interconnects for semiconductor packages are described. An apparatus may comprise a decoupling capacitor on a logic board, and a conductive interconnect element on the logic board, the conductive interconnect element to connect the decoupling capacitor on the logic board to a power conductor comprising a power pad of a semiconductor package, the conductive interconnect element at a different layer than a ground-potential layer of the logic board. Other embodiments are described and claimed.
US10163765B2
A semiconductor device includes a semiconductor chip having a terminal thereon, a lead frame for connection to an external device, a bonding wire connecting the terminal of the semiconductor chip and the lead frame. A mold resin layer encloses the semiconductor chip and the bonding wire, such that a portion of the lead frame extends out of the mold resin layer. A molecular bonding layer has a portion on a surface of the bonding wire and includes a first molecular portion covalently bonded to a material of the bonding wire and a material of the mold resin layer.
US10163753B2
A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer. The method also includes forming a catalyst layer over a sidewall of the opening and forming a conductive element directly on the catalyst layer. The catalyst layer is capable of lowering a formation temperature of the conductive element. The method further includes removing a portion of the conductive element such that the conductive element is within a space surrounded by the catalyst layer.
US10163749B2
A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that has larger tensile stress and a second insulation film that has smaller tensile stress. Each of the first insulation film and the second insulation film is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film. The passivation film as a whole generates tensile stress.
US10163731B2
A FinFET semiconductor structure includes first fins and second fins extended from a semiconductor substrate, and a gate structure disposed over the first fins and the second fins. Each first fin includes a first semiconductor portion connected to the semiconductor substrate and a second semiconductor portion over the semiconductor substrate. Each second fin includes the first semiconductor portion connected to the semiconductor substrate, the second semiconductor portion, and at least one spacer at least partially disposed between the first semiconductor portion and the second semiconductor portion. The semiconductor substrate and the first semiconductor portion respectively have a surface oriented on a first crystal plane, the second semiconductor portion has a surface oriented on a second crystal plane, wherein the first crystal plane is oriented differently than the second crystal plane.
US10163727B2
A device includes a semiconductor substrate, a first Metal-Oxide-Semiconductor (MOS) device, and a second MOS device of a same conductivity as the first MOS device. The first MOS device includes a first gate stack over the semiconductor substrate, and a first stressor adjacent to the first gate stack and extending into the semiconductor substrate. The first stressor and the first gate stack have a first distance. The second MOS device includes a second gate stack over the semiconductor substrate, and a second stressor adjacent to the second gate stack and extending into the semiconductor substrate. The second stressor and the second gate stack have a second distance greater than the first distance.
US10163723B2
A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate.
US10163710B2
A method of forming a semiconductor package includes depositing a passivation layer overlying a semiconductor substrate, wherein the semiconductor substrate includes a scribe line region positioned between a first chip region and a second chip region. The method further includes forming a bump overlying the passivation layer on at least one of the first chip region or the second chip region, wherein the bump comprises a copper pillar and a cap layer. The method further includes forming a groove passing through the passivation layer on the scribe line region, wherein the groove extends into the semiconductor substrate to expose a stepped sidewall of the semiconductor substrate. The method further includes applying a molding compound layer to cover the passivation layer and a lower portion of the bump and fill the groove. The method further includes singulating along the scribe line region.
US10163708B2
Some embodiments relate to a semiconductor module having an integrated antenna structure. The semiconductor module has an excitable element and a first ground plane disposed between a substrate and the excitable element. A second ground plane is separated from the first ground plane by the substrate. The second ground plane is coupled to the first ground plane by one or more through-substrate vias (TSVs) that extend through the substrate.
US10163704B2
A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a π-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.
US10163703B2
A method for forming a self-aligned contact is provided. In an embodiment, a metal gate is formed on a substrate, and a gate spacer is formed adjacent the metal gate. A conductive plug is formed over the substrate, with the gate spacer disposed between the metal gate and the conductive plug. The metal gate and the conductive plug are recessed. A first dielectric layer is deposited over the gate spacer, over the metal gate, over the conductive plug, and along sidewalls of the metal gate. A first opening is formed in the first dielectric layer exposing the metal gate, and a second opening is formed in the first dielectric layer exposing the conductive plug. The first opening and the second opening are filled with a first conductive material.
US10163696B2
Exemplary methods for removing cobalt material may include flowing a chlorine-containing precursor into a processing region of a semiconductor processing chamber. The methods may include forming a plasma of the chlorine-containing precursor to produce plasma effluents. The methods may also include contacting an exposed region of cobalt with the plasma effluents. The exposed region of cobalt may include an overhang of cobalt on a trench defined on a substrate. The plasma effluents may produce cobalt chloride at the overhang of cobalt. The methods may include flowing a nitrogen-containing precursor into the processing region of the semiconductor processing chamber. The methods may further include contacting the cobalt chloride with the nitrogen-containing precursor. The methods may also include recessing the overhang of cobalt.
US10163690B2
Two-dimensional (2-D) interconnects in a one-dimensional (1-D) patterning layout for integrated circuits is disclosed. This disclosure provides methods of connecting even or odd numbered lines that are in the x-direction of a 1-D patterning layout through 2-D interconnects in the y-direction. Depending on device design needs, 2-D interconnects may be perpendicular or non-perpendicular to the even or odd numbered lines. The freedom of two-dimensional patterning compared to conventional self-aligned multiple patterning (SAMP) processes used in the 1-D patterning processes is provided. The two-dimensional patterning described herein provides line widths that match the critical dimensions in both x and y directions. The separation between the 1-D lines or between 2-D interconnects and the end of 1-D lines can be kept to a constant and at a minimum.
US10163687B2
A package may include a die proximate to a structure having a substrate with interconnects and a first component coupled to the interconnects. The die may be face up or face down. The package may include a first redistribution layer coupling the die to the interconnects of the structure and a mold compound covering the die and maybe the structure.
US10163684B2
A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.
US10163677B2
Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.
US10163675B2
Methods and apparatuses for stacking devices in an integrated circuit assembly are provided. A tray for supporting multiple dies of a semiconductor material enables both topside processing and bottom side processing of the dies. The dies can be picked and placed for bonding on a substrate or on die stacks without flipping the dies, thereby avoiding particulate debris from the diced edges of the dies from interfering and contaminating the bonding process. In an implementation, a liftoff apparatus directs a pneumatic flow of gas to lift the dies from the tray for bonding to a substrate, and to previously bonded dies, without flipping the dies. An example system allows processing of both top and bottom surfaces of the dies in a single cycle in preparation for bonding, and then pneumatically lifts the dies up to a target substrate so that topsides of the dies bond to bottom sides of dies of the previous batch, in an efficient and flip-free assembly of die stacks.
US10163669B2
A method for thickness measurement includes forming an implantation region in a semiconductor substrate. A semiconductor layer is formed on the implantation region of the semiconductor substrate. Modulated free carriers are generated in the implantation region of the semiconductor substrate. A probe beam is provided on the semiconductor layer and the implantation region of the semiconductor substrate with the modulated free carriers therein. The probe beam reflected from the semiconductor layer and the implantation region is detected to determine a thickness of the semiconductor layer.
US10163666B2
Provided is a temperature control system configured to mix a low temperature heating medium and a high temperature heating medium to supply the heating mediums at a temperature according to a process recipe to an electrostatic chuck (ESC) configured to maintain a temperature and support a wafer in a chamber in which a semiconductor wafer processing process is performed, and a heating medium obtained by mixing a heating medium cooled through a thermoelectric element and a heating medium heated through a heater to a desired target temperature according to a first ratio and a second ratio is provided to a load and recovered from the load, and the heating medium is distributed to the thermoelectric element and the heater according to the first ratio and the second ratio, which are ratios upon the mixing, optimizing power consumption for cooling or heating.
US10163664B2
A substrate cleaning apparatus (50) that cleans a substrate (S) includes: circumference supporting members (51) that support and rotate the substrate (S); a sponge (541) having a cleaning surface that is brought into contact with the surface to be cleaned of the substrate (S) being rotated by the circumference supporting members (51), and cleans the surface to be cleaned; an arm (53) that moves the sponge (541) in a radial direction of the substrate (S) while maintaining the cleaning surface in contact with the surface to be cleaned; and a controller (60) that controls the contact pressure of the cleaning surface on the surface to be cleaned. When the sponge (541) is located near the edge of the substrate (S), the controller (60) adjusts the contact pressure to a smaller value than that of when the sponge (541) is located near the center of the substrate (S).
US10163655B2
Apparatuses and methods are disclosed herein for densification of through substrate insulating liners. An example method may include forming a through substrate via through at least a portion of a substrate, forming a first liner layer in the through substrate via, and densifying the first liner layer. The example method may further include forming a second liner layer on the first liner layer, and densifying the second liner layer.
US10163653B2
A plasma etching method for plasma-etching an object including an etching target film and a patterned mask. The plasma etching method includes a first step of plasma-etching the etching target film using the mask, and a second step of depositing a silicon-containing film using plasma of a silicon-containing gas on at least a part of a side wall of the etching target film etched by the first step.
US10163652B2
The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first cut pattern in a first hard mask layer formed over the patterning-target layer; forming a second cut pattern in a second hard mask layer formed over the patterning layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the second cut pattern in the second hard mask layer and a portion of the patterning-target layer within a first trench; and selectively removing a portion of the first cut pattern in the first hard mask layer and a portion of the patterning-target layer within a second trench.
US10163651B1
A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends upwardly along sidewalls of the bottom electrode, the switching dielectric, and the top electrode. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The lower etch stop layer is made of a material different from the sidewall spacer layer and protects the top electrode from damaging during manufacturing processes. A method for manufacturing the memory cell is also provided.
US10163647B2
A method for forming a deep trench structure is provided. The method includes forming a first recess in a top portion of a substrate and forming a first protective layer on sidewalls of the first recess. The method includes etching a middle portion of the substrate by using the first protective layer as a mask to form a second recess and forming a second protective layer on sidewalls of the second recess. The method also includes etching a bottom portion of the substrate by using the second protective layer as a mask to form a third recess; and removing the first protective layer and the second protective layer to form a deep trench structure. The deep trench structure is constructed by the first recess, the second recess and the third recess, and the deep trench structure has a stair shape.
US10163645B2
There are provided a processing method for a wide-bandgap semiconductor substrate and an apparatus therefor that use no abrasives or no abrasive grains, or no solution having a large environmental burden at all, can process a single crystal, which is SiC, GaN, AlGaN, or AlN, at a variety of processing speed, can obtain a surface of higher quality than the quality of a surface finished by CMP, and also have an excellent compatibility with a clean room. A catalytic substance having a function of promoting the direct hydrolysis of a work piece (5) or promoting the hydrolysis of an oxide film on the surface of the work piece is used as a processing reference plane (3). In the presence of water (1), the work piece is brought into contact with or extremely close to the processing reference plane at a predetermined pressure.
US10163633B2
Methods of forming non-mandrel cuts. A dielectric layer is formed on a metal hardmask layer, and a patterned sacrificial layer is formed on the dielectric layer. The dielectric layer is etched to form a non-mandrel cut in the dielectric layer that is vertically aligned with the opening in the patterned sacrificial layer. A metal layer is formed on an area of the metal hardmask layer exposed by the non-mandrel cut in the dielectric layer. The metal hardmask layer is patterned with the metal layer masking the metal hardmask layer over the area.
US10163629B2
Systems and methods for processing films on the surface of a substrate are described. The systems possess aerosol generators which form droplets from a condensed matter (liquid or solid) of one or more precursors. A carrier gas is flowed through the condensed matter and push the droplets toward a substrate placed in a substrate processing region. An inline pump connected with the aerosol generator can also be used to push the droplets towards the substrate. A direct current (DC) electric field is applied between two conducting plates configured to pass the droplets in-between. The size of the droplets is desirably reduced by application of the DC electric field. After passing through the DC electric field, the droplets pass into the substrate processing region and chemically react with the substrate to deposit or etch films.
US10163627B2
A semiconductor device includes a substrate, a first dielectric layer, a first semiconductor layer, a second dielectric layer and a second semiconductor layer. The first dielectric layer is disposed on the substrate and includes at least one first trench formed in the first dielectric layer. The first semiconductor layer is disposed on the first dielectric layer and within the at least one first trench. The second dielectric layer is disposed on the first semiconductor layer and includes at least one second trench formed in the second dielectric layer, wherein in a planar view, the at least one first trench and the at least one second trench are not overlapped with each other. The second semiconductor layer is disposed on the second dielectric layer and within the at least one second trench.
US10163626B2
An NMOS transistor gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region and lining an inner sidewall of the spacer, a bottom barrier layer conformally disposed on the gate dielectric layer, a work function metal layer disposed on the bottom barrier layer, and a filling metal partially wrapped by the work function metal layer. The bottom barrier layer has an oxygen concentration higher than a nitrogen concentration. The bottom barrier layer is in direct contact with the gate dielectric layer. The bottom barrier layer includes a material selected from Ta, TaN, TaTi, TaTiN and a combination thereof.
US10163621B1
A semiconductor device and a method of forming the same are disclosed. The method includes receiving a semiconductor substrate and a fin extending from the semiconductor substrate; forming multiple dielectric layers conformally covering the fin, the multiple dielectric layers including a first charged dielectric layer having net fixed first-type charges and a second charged dielectric layer having net fixed second-type charges, the second-type charges being opposite to the first-type charges, the first-type charges having a first sheet density and the second-type charges having a second sheet density, the first charged dielectric layer being interposed between the fin and the second charged dielectric layer; patterning the multiple dielectric layers, thereby exposing a first portion of the fin, wherein a second portion of the fin is surrounded by at least a portion of the first charged dielectric layer; and forming a gate structure engaging the first portion of the fin.
US10163616B2
A multi-reflecting time-of-flight mass spectrometer comprises a pair of parallel aligned ion mirrors and a set of periodic lenses for confining ion packets along the drift z-direction. To compensate for time-of-flight spherical aberrations T|zz created by the periodic lenses, at least one set of electrodes are disposed within the apparatus, forming an accelerating or reflecting electrostatic fields which are curved in the z-direction in order to form local negative T|zz aberration. The structure may be formed within an accelerator, within flinging fields or intentionally and locally curved fields of ion mirrors, within electrostatic sector interface, or at curved surface of ion to electron converter at the detector.
US10163606B2
An annular lid plate of a plasma reactor has upper and lower layers of gas distribution channels distributing gas along equal length paths from gas supply lines to respective gas distribution passages of a ceiling gas nozzle.
US10163603B2
A particle beam system includes a particle source to produce a first beam of charged particles. The particle beam system also includes a multiple beam producer to produce a plurality of partial beams from a first incident beam of charged particles. The partial beams are spaced apart spatially in a direction perpendicular to a propagation direction of the partial beams. The plurality of partial beams includes at least a first partial beam and a second partial beam. The particle beam system further includes an objective to focus incident partial beams in a first plane so that a first region, on which the first partial beam is incident in the first plane, is separated from a second region, on which a second partial beam is incident. The particle beam system also a detector system including a plurality of detection regions and a projective system.
US10163599B1
An electron multiplier for a Micro-Electro-Mechanical-Systems (MEMS) image intensifier includes an input surface, an emission surface, a plurality of doped ribs, and a plurality of textured surfaces. The input surface receives electrons and the emission surface is opposite the input surface. The plurality of doped ribs extends at least partially between the input surface and the emission surface to form a plurality of pixels. The plurality of textured surfaces are disposed in the plurality of pixels.
US10163593B2
A temperature switch 1 includes first terminal unit 2 having a first terminal 5 and a first fixed contact 6, a switch body unit 3 including a bimetal element 22 in which both ends engage a movable plate 15 holding, via an tongue portion 17, first and second fixed contacts 6 and 8 arranged in an internal center portion of an insulation material 10 at prescribed intervals and also holding a movable contact 18 arranged above them, and a second terminal unit 4 having a second terminal 7 and the second fixed contact 8. The first terminal unit 2, the switch body unit 3, and the second terminal unit 4 are sequentially arranged in line. At an ambient temperature, the bimetal element 22 deforms into a convex shape in the contact direction so as to push out the tongue portion 17 and the movable contact 18 at the center of the convex shape, and the movable contact 18 is closed with respect to the first and second fixed contacts 6 and 8 so that a current flows between the first and second terminals 5 and 7. At an ambient temperature equal to or higher than a prescribed value, the bimetal element 22 causes inversion to become concave in the contact direction, releases the biasing force of the spring property toward the space above the tongue portion 17, the movable contact 18 moves away from the first and second fixed contacts 6 and 8, and a current is cut off.
US10163592B2
An equipment isolation switch assembly (200) for use in a remote isolation system (10) for isolating an equipment item (20,21) comprising an equipment isolation switch (400) movable between a first position (NORMAL) in which said equipment item (20,21) is energized by an energy source (30) and a second isolated position (ISOLATE) in which said equipment item (20,21) is isolated from said energy source (30) and an actuating device (500) co-operable with the equipment isolation switch (400) to move it between said first and second positions wherein said isolation switch assembly (200) includes at least one securing means (291,405) for securing said actuating device (500) in co-operation with said equipment isolation switch (400) whenever in operative state.
US10163578B2
An oxadiazole dye for use as an organic photosensitizer. The oxadiazole dye comprising donor-π-spacer-acceptor type portions in which at least one of an oxadiazole isomer acts as a π-conjugated bridge (spacer), a biphenyl unit acts as an electron-donating unit, a carboxyl group act as an electron acceptor group, and a cyano group acts as an anchor group. An optional thiophene group acts as part of the π-conjugated bridge (spacer). The dye for use as organic photosensitizers in a dye-sensitized solar cell and in photodynamic therapies. Computational DFT and time dependent DFT (TD-DFT) modeling techniques showing Light Harvesting Efficiency (LHE), Free Energy for Electron Injection (ΔGinject), Excitation Energies, and Frontier Molecular Orbitals (FMOs) indicate that the series of dye comprise a more negative ΔGinject and a higher LHE value; resulting in a higher incident photon to current efficiency (IPCE).
US10163573B1
A capacitor assembly includes a capacitor having ends. A terminal covers less than an area of one end. A wire bond has opposing ends with one end being coupled to the terminal and is configured to break connection with a circuit when an electrical current through the wire bond reaches a fusing current. An energy storage module includes at least two capacitor assemblies. The wire bond of one capacitor is electrically connected to the second terminal of an adjacent capacitor. An energy storage assembly includes two energy storage modules stacked one on top of the other. A pulse forming network includes conductors and at least two energy storage modules. A method of making a module includes charging each of the capacitors, removing each capacitor that fails, connecting one end of a wire bond to one terminal and connecting the other end to an adjacent capacitor or to a conductor.
US10163568B2
There is provided a multilayer ceramic capacitor including a ceramic body including a plurality of dielectric layers and having first and second main surfaces opposing each other, first and second side surfaces opposing each other, and first and second end surfaces opposing each other, a plurality of internal electrodes having the dielectric layer interposed therebetween, electrode layers formed on the first and second end surfaces of the ceramic body and electrically connected to the plurality of internal electrodes, and an impact absorption layer formed on the electrode layer so that an edge thereof is exposed.
US10163565B2
The present invention is related to a method for winding a dual-layer flat wire coil, and to method for winding a multi-layer flat wire coil. Furthermore, the present invention is related to a device for winding such coils and to a dual-layer flat wire coil and to a multi-layer flat wire coil obtainable by performing the method of the present invention. Finally, the invention is related to a linear motor comprising such a dual-layer flat wire coil and/or multi-layer flat wire coil. According to the invention, an auxiliary winding core is used to temporarily store wire that is intended to form the odd layer of any pair of layers in the multi-layer coil.
US10163560B2
A coil device, in which an air-core coil of a cylindrical shape is buried in a core including a magnetic powder and a resin, showing, CV value of the below described cross sectional areas, SA1 to SA5, 0.55 or less, when an outer diameter of the air-core coil is “a1”, an inner diameter of the same is “a2”, and a distance between a surface of the core perpendicular to a direction of winding axis and an end of the air-core coil in the direction of winding axis is “h”, is provided. The coil device is superior in DC superimposing characteristic while suppressing the magnetic saturation.
US10163557B2
Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.
US10163554B2
A transformer includes a magnetic core, a first coil unit and a second coil unit. The first coil unit is disposed within the magnetic core and includes a laminated board having layers laminated therein and conductive patterns. Respective ones of the conductive patterns are disposed on the laminated layers. The second coil unit includes a conductive wire spaced apart from the conductive patterns of the laminated board by an insulating distance. The conductive wire includes a triple-insulated wire surrounded by three sheets of insulating paper to maintain the insulating distance from the conductive patterns.
US10163551B2
A method of manufacturing a coated conducting wire assembly includes forming a conducting wire assembly by twist-deforming a conducting wire bundle, forming a coated conducting wire assembly by covering the conducting wire assembly with an insulation coating, and annealing the coated conducting wire assembly. The conducting wire bundle is formed by bundling a plurality of conducting wires. The conducting wire assembly includes a parallel portion, a left-wound portion, and a right-wound portion. The annealing is performed by heating and holding the coated conducting wire assembly at an annealing temperature while applying tension to the covered conducting wire assembly.
US10163548B2
The present disclosure relates to a hybrid cable having a jacket with a central portion positioned between left and right portions. The central portion contains at least one optical fiber and the left and right portions contain electrical conductors. The left and right portions can be manually torn from the central portion.
US10163547B2
A composite cable includes: a plurality of first electric wires; a shield wire including a twisted wire in which a plurality of second electric wires are twisted together and a shield layer provided on an outer periphery of the twisted wire, each of the second electric wires having an outer diameter smaller than each of the first electric wires; a sheath provided on an outer periphery of an electric wire bundle in which the plurality of first electric wires and the shield wire are twisted together; a plurality of first linear fillers filled between the twisted wire and the shield layer; and a plurality of second linear fillers filled between the electric wire bundle and the sheath, wherein each of the first linear fillers and each of the second linear fillers are a same type of linear filler, and a fill ratio of the first linear fillers is greater than a fill ratio of the second linear fillers.
US10163544B2
A wire harness includes a conductive path including a braided part and a sheath member accommodating the conductive path so as to protect the conductive path. The braided part is provided as an outermost layer of the conductive path. The braided part includes a cushion part having elasticity in a radial direction of the conductive path and projecting outward in the radial direction toward the sheath member.
US10163542B2
The method of manufacturing a natural ester, oil-based electrical insulation fluid by contacting refined, bleached, optionally winterized, and deodorized natural ester oil, e.g., soy oil, with an absorbent is improved by using as the absorbent a synthetic silicate absorbent comprising an alkali and/or alkaline earth metal, e.g., magnesium.
US10163527B2
Techniques for generating a user interface for monitoring biometric data. Embodiments generate a first portion of the user interface by plotting values of a first biometric parameter on a first graph structure with respect to a first interval of time and generate a second portion of the user interface by plotting values of a second biometric parameter on a second graph structure with respect to a second interval of time that overlaps with only a portion of the first interval of time. Upon receiving a user selection specifying a first position within the first graph structure, embodiments determine a third interval of time that is centered at a moment in time corresponding to the specified first position and update the second graph structure by plotting a third plurality of values of the second biometric parameter on the second graph structure, with respect to the third interval of time.
US10163526B2
The present disclosure relates to a structure which includes a twin-cell memory which is configured to program a plurality of write operations, a current sense amplifier which is connected to the twin-cell memory and is configured to sense a current differential and latch a differential voltage based on the current differential, and at least one current source which is connected to the current sense amplifier and is configured to add an offset current to the current sense amplifier to create the differential voltage.
US10163521B2
A bootstrapped sampling switch may be used at lower supply voltages due to its high linearity, wherein the sampled voltage may be substantially higher than the supply voltage. A 2.7 volt or lower DC supply may be used with this sampling switch to sample a much higher voltage. A plurality of these high voltage transmission gate switches may be connected directly together, thereby removing a primary source of channel-to-channel mismatch (the active buffer/voltage reduction circuit) and enables new methods of error compensation not previously possible. The sampling switch circuit does not consume DC current from what is being measured. There may be a small switched capacitor voltage charge and there may be some voltage leakage, but no DC current is drawn from the voltage input being measured.
US10163518B2
Provided is a read method for a nonvolatile memory device for reading data with an optimum read voltage. The read method includes reading data of a first set of memory cells connected to a first word line, by dividing the data of the first set of memory cells into M pages and individually reading data from the M pages. The reading data includes performing an on-chip valley search (OVS) operation on a first valley of two adjacent threshold voltage distributions of the first set of memory cells when reading each of the M pages, and performing a data recover read operation via a read operation on a second word line adjacent to the first word line, based on a result of the OVS operation. In the data recover read operation, a read operation on the first word line is not performed.
US10163517B2
A semiconductor memory device includes first, second, and third memory cells, and first, second, and third word lines that are respectively connected to gates of the first, second, and third memory cells. A control circuit executes first, second, and third read operations in response to first, second, and third command sets, respectively. The first read operation includes a first read sequence, in which the control circuit reads data by applying first to third voltages to the first word line. In the second read operation, the control circuit reads data by applying a second read voltage that is set based on a result of the first read sequence, to the second word line. In the third read operation, the control circuit reads data from the third memory cells by applying a second read voltage that is set independently of the result of the first read sequence, to the third word line.
US10163511B2
A nonvolatile memory device includes a memory cell array, a row decoder circuit, a page buffer circuit, and a control logic circuit. The control logic circuit controls the row decoder circuit and the page buffer circuit to perform: (1) a pre-program of sequentially selecting a plurality of memory blocks and increasing threshold voltages of string selection transistors or ground selection transistors of the selected memory block and (2) after the pre-program is completed, a main program of sequentially selecting the plurality of memory blocks, programming string selection transistors or ground selection transistors of the selected memory block, and performing a verification by using a verification voltage.
US10163507B1
Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
US10163505B2
A resistive random access memory (RRAM) circuit is provided. In some embodiments, the RRAM circuit has a plurality of RRAM cells. A bit-line decoder is configured to concurrently apply a forming signal to the plurality of RRAM cells. A current limiting element is configured to concurrently limit a current of the forming signal applied to the plurality of RRAM cells.
US10163499B2
A control device for writing data into a flash memory unit includes a determining circuit and a writing circuit. The determining circuit is arranged to determine a data polarity of an n-th data bit of the flash memory unit when writing data into the flash memory unit for the n-th time. The writing circuit is arranged to inject an n-th electrical charge amount to a floating gate of the flash memory unit according to the data polarity of the n-th data bit only. The determining circuit is further arranged to determine the data polarity of an (n+1)-th data bit of the flash memory unit when writing data into the flash memory unit for the (n+1)-th time. The writing circuit is further arranged to selectively inject an (n+1)-th electrical charge amount to the floating gate of the flash memory unit according to the data polarity of the (n+1)-th data bit only.
US10163493B2
Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.
US10163485B2
A memory module includes a memory interface circuit and a training signal generator. The memory interface circuit includes a plurality of terminals for communicating with a memory controller, and the terminals comprise at least a plurality of data terminals. The training signal generator is coupled to the memory interface circuit, and is arranged for generating a training signal to the memory controller through only a portion of the data terminals or a specific terminal instead of the data terminals when the memory module receives a training request from the memory controller.
US10163476B2
A method of operating a tracking circuit of a memory device includes charging a node of the tracking circuit to a first predetermined voltage level, the first node being electrically coupled with a first load device. A first plurality of tracking cell transistors are activated to discharge the first node toward a second predetermined voltage level. A reset signal is generated based on a signal at the first node. The reset signal may correspond to a waiting period for reading a memory cell of the memory device.
US10163470B2
A dual rail memory operable at a first voltage and a second voltage is disclosed. The dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal, wherein the data path includes a first level shifter for transferring the input data signal from the second voltage to the first voltage; and a control circuit configured to provide control signals to the memory array, the word line driver circuit and the data path, wherein the control circuit includes a second level shifter for transferring an input control signal from the second voltage to the first voltage; wherein the data path and the control circuit are configured to operate at both the first and second voltages.
US10163464B2
A memory module may be provided. The memory module may include a thermocouple and a temperature sensor. The thermocouple may be coupled to at least one contact point among a plurality of contact points formed on a region, on which a memory device may be configured to be mounted. The temperature sensor may be coupled to the thermocouple, and may be configured to generate temperature information.
US10163454B2
A method is provided for training a Deep Neural Network (DNN) for acoustic modeling in speech recognition. The method includes reading central frames and side frames as input frames from a memory. The side frames are preceding side frames preceding the central frames and/or succeeding side frames succeeding the central frames. The method further includes executing pre-training for only the central frames or both the central frames and the side frames and fine-tuning for the central frames and the side frames so as to emphasize connections between acoustic features in the central frames and units of the bottom layer in hidden layer of the DNN.
US10163452B2
An electronic device including a voice obtaining microphone configured to receive a voice signal including a noise at a first level; a noise obtaining microphone configured to receive a voice signal including a noise at a second level higher than the first level; and a controller configured to estimate the noise at the second level from the voice signal received by the noise obtaining microphone, remove the noise at the first level from the voice signal received by the voice obtaining microphone based on the estimated noise, and perform an operation corresponding to the voice signal having the noise at the first level eliminated therefrom.
US10163451B2
Techniques for accent translation are described herein. A plurality of audio samples may be received, and each of the plurality of audio samples may be associated with at least one of a plurality of accents. Audio samples associated with at least a first accent of the plurality of accents may be compared to audio samples associated with at least one other accent of the plurality of accents. A translation model between the first accent and a second accent may be generated. An input audio portion in a first spoken language may be received. It may be determined whether the input audio portion is substantially associated with the first accent, and if so, an output audio portion substantially associated with the second accent in the first spoken language may be outputted based, at least in part, on the translation model.
US10163436B1
Systems, methods, and devices for training a Natural Language Understanding (NLU) component of a system using spoken utterances of individuals are described. A server sends a device, such as a speech-controlled device, a signal that causes the device to output audio soliciting content regarding how a user would speak a particular command for execution by a particular application. The device captures spoken audio and sends it to the server. The server performs speech processing on received audio data to parse the audio data into multiple portions. The server then associates a first portion of the audio data with a command indicator and a second portion of the audio data with a content indicator. The associated data is then used to update how the NLU component determines how utterances triggering the command are spoken.
US10163433B2
An automotive active brake noise damping system to actively damp braking noise perceivable in the passenger compartment of a motor vehicle comprising a braking system comprising a plurality of braking assemblies associated with wheels of the motor vehicle. The automotive active brake noise damping system comprises a sensory system to sense quantities that allow braking noise perceived in the passenger compartment of the motor vehicle and generated by the braking assemblies during braking to be estimated, an audio system to diffuse sounds in the passenger compartment of the motor vehicle, and an electronic control unit connected to the sensory system and the audio system, and programmed to control the audio system based on the quantities sensed by the sensor system to actively damp the braking noise perceived in the passenger compartment of the motor vehicle. The sensory system comprises vibration sensors, conveniently in the form of piezoelectric accelerators, which are applied to the braking assemblies to sense the amplitude of the vibrations generated by the braking assemblies during braking, and the electronic control unit is programmed to store a mathematical model, which correlates vibrations generated by the braking assemblies during braking with corresponding braking noise perceived in the passenger compartment of the motor vehicle and produced by the braking assemblies during braking, estimate the braking noise perceived in the passenger compartment of the motor vehicle and generated by the braking assemblies of the braking system during braking as a function of the vibrations generated by the braking assemblies during braking and sensed by the vibration sensors applied to the braking assemblies and of the stored mathematical model, compute an interfering sound to be diffused in the passenger compartment of the motor vehicle to damp the braking noise perceived in the passenger compartment of the motor vehicle and generated by the braking assemblies during braking, and control the audio system to cause it to diffuse the computed interfering sound.
US10163432B2
A system and method (referred to as the system) that actively reduces noise in a vehicle. The system generates one or more control output signals to drive multiple loudspeakers; and adapts multiple control coefficients of a control filter based on multiple secondary path transfer functions. The secondary path transfer functions model the acoustic paths between each loudspeaker and multiple microphones. The multiple control coefficients are time varying and frequency dependent and the rate the plurality control coefficients adapt is based on an adaptive step size based on one or more step size criteria.
US10163428B2
Synthetic multi-string musical instruments have been developed for capturing and rendering musical performances on handheld or other portable devices in which a multi-touch sensitive display provides one of the input vectors for an expressive performance by a user or musician. Visual cues may be provided on the multi-touch sensitive display to guide the user in a performance based on a musical score. Alternatively, or in addition, uncued freestyle modes of operation may be provided. In either case, it is not the musical score that drives digital synthesis and audible rendering of the synthetic multi-string musical instrument. Rather, it is the stream of user gestures captured at least in part using the multi-touch sensitive display that drives the digital synthesis and audible rendering.
US10163427B1
A percussion musical instrument constructed to be played by striking the instrument with one or both of a person's feet comprising a body having at least one surface area to which is affixed at least one snare mechanism bearing on the surface area in a manner to be responsive to the striking of the feet on a second surface area of the body.
US10163425B2
A chuck structure for fixing a drumstick on a non-circular revolving shaft of a foot drum includes a retractable chuck, two arched plates and a fastening element. The two arched plates clamp the non-circular revolving shaft. An inner arched surface of each arched plate has an inner fastening surface correspondingly clamping the non-circular revolving shaft, and an outer arched surface of each arched plate has a spiked surface. The retractable chuck includes a fastening portion and a rotating portion, which are pivotally connected to each other, clamp the two arched plates, and are penetrated by the drumstick. Each of the fastening portion and a rotating portion has a clamping surface abutting against the spiked surface. The fastening member propels and rotates the rotating portion, so as to allow the retractable chuck, spaced by the two arched plates, to clamp and fasten on the non-circular revolving shaft.
US10163421B2
The present disclosure provides an automatic parameter adjustment system and an automatic parameter adjustment method for a display device, and the display device. The automatic parameter adjustment system includes a body state detector configured to detect a body state parameter of a user, and a controller configured to acquire the body state parameter and adjust a parameter of the display device in accordance with the body state parameter.
US10163408B1
A method includes determining a display backlight level based upon an ambient light level, using image content of incoming image data to adjust the display backlight level based upon image content to produce an image-compensated backlight value, and adjusting pixel values in the image data as needed based upon the image-compensated backlight value.
US10163398B2
A method of driving a display panel includes adjusting a level of a data sustaining voltage or an on bias voltage during an on bias compensating period, applying the on bias voltage to pixels through data lines during an on bias period, which is subsequent to the on bias compensating period, to adjust a voltage level of control electrodes of driving transistors of the pixels, initiating a voltage of anode electrodes of organic light emitting elements of the pixels during an initiating period, applying data voltages to the pixels through the data lines during a scanning period, and turning on the organic light emitting elements of the pixels during an emission period.
US10163397B2
A pixel unit includes a first organic light emitting diode for a front-side emission, a second organic light emitting diode for a back-side (both-sides) emission, and a pixel circuit configured to driver the first and second organic light emitting diodes. The pixel unit PU may include a pixel circuit, a first organic light emitting diode and a second organic light emitting diode.
US10163386B2
Disclosed is a display device that can rapidly recover from a fail situation. The display device includes: a display panel; a source drive IC configured to supply a data signal to the display panel and including a calibrating unit; a timing controller configured to supply a data control signal and a frame data to the source drive IC; and a common bus line formed between the source drive IC and the timing controller. The calibrating unit sets and stores a calibration value in response to the data control signal during an initialization period before receiving the frame data from the timing controller, and transmits the calibration value to the timing controller through the common bus line.
US10163371B1
Generating non-compressible data streams is disclosed, including: receiving a sequence comprising a plurality of byte values calculated from an initialization parameter and a constrained prime number; determining a data structure index from a plurality of bits within at least one of the plurality of byte values; retrieving a rotation value from a data structure, wherein the rotation value is stored in the data structure at the data structure index; and rotating a portion of the sequence based on a rotation value to form a rotated sequence, wherein the rotated sequence comprises byte values substantially defeating a predictive compression algorithm.
US10163362B2
A feeling of each of members forming a group or team and the mood of all the members felt by each member are objectified and recorded. An emotion/mood data input, display, and analysis device includes a controller, a display, an input unit, and a recording unit. The controller includes an input screen generation unit. The input screen generation unit generates a first input screen that allows each of multiple members forming a group to, as an inputter, input whether an emotion or feeling of the each member is cheerful or gloomy, a level of cheerfulness or gloominess, whether the emotion or feeling is strong or weak, and a level of strength or weakness in a bifurcated manner. The display displays the first input screen. The controller captures data through the first input screen displayed on the display and the input unit and records the data in the recording unit.
US10163359B2
A system, method, and computer program product for presenting a video. A method of the present invention includes a link-map, where the link-map comprises one or more segments and one or more links between segments and where each link is associated with a user category. The method further includes retrieving a current segment to play for a user associated with a user category. The retrieving includes traversing a link of the link-map based on the user category. The retrieving further includes selecting the current segment to play from the plurality of segments based on traversing the link-map. The method further includes playing the current segment. The method further includes repeating the retrieving and playing steps until an end condition is reached.
US10163352B2
When performing a switch between the lane change control and the lane keeping control, a switching controller of the driving control device sets a transition time-frame for performing the switch, and gradually switches between the lane change control and the lane keeping control during the transition time-frame.
US10163334B1
A system and method for controlling the operation of a vacuum material handler providing secure communication between the wireless remote control and the receiver of a controller on the vacuum material handler. The system providing a haptic confirmation of a valid command. The system also providing a battery life extending sleep mode when left inactive for a predetermined length of time. The system further including a pendant remote in communication with the wireless remote control. The pendant remote being operable to command the vacuum material handler.
US10163329B1
Techniques are described for selecting an alarm state based at least in part on determining a security event related to security and automation systems. One method includes receiving, from a sensor, a first indication of a security event at the first location, determining a first threat level based on the security event, and activating a first alarm state based at least in part on the first threat level.
US10163316B2
Methods and systems for detection of removable vehicle seats may be used to indicate presence or absence of a child in the vehicle. In some examples, an alarm system includes a radio frequency (RF) transceiver and a removable seat magnetic coupling. Various actions are triggered when the parent (e.g., guardian) goes beyond a predefined range while the removable seat is within the vehicle, such as sounding an alarm on a mobile electronic device.
US10163313B2
A system and method to detect an event by analyzing sound signals received from a plurality of configured sensors. The sensors can be fixed or mobile and sensor activity is tracked in a sensor map. The frame analyzer of the system compares sound signals received from the sensors and applies knowledge data to determine if any deviation observed can be determined to be an uncharacteristic event. A rule data set comprising priority data, type of event, location is applied to the output of the frame analyzer to determine if the uncharacteristic sound observed is an event. On detection of an event, alerts are issued to appropriate authority. Further, sound frame and contextual data associated with the event are stored to serve as continuous learning for the system.
US10163307B1
A depository system operates in response to data bearing records. Information regarding planned future deposits is recorded, at least one record visible appearance feature is stored or generated, and data corresponding to the at least one record appearance feature is stored in associated relation with deposit data. The at least one record appearance feature is made visible on a deposit item. The deposit item is subsequently presented to a depository that includes an image sensor. The image sensor operates to read the at least one record appearance feature. At least one controller in the depository causes a determination to be made that at least one record appearance feature corresponds to a pre-registered deposit and such determination enables the deposit item to be received in the depository.
US10163302B2
A gaming system which enables a player to purchase an amount of virtual currency from an online casino wherein the purchased virtual currency includes a predetermined component and a variable component.
US10163298B2
A wagering game system and its operations are described herein. In some embodiments, the operations can include detecting that one or more wearable computers are within a proximity range to a wagering game machine. In some examples, the operations further include determining one or more characteristics associated with the one or more wearable computers in response to the detecting that the one or more wearable computers are within the proximity range to the wagering game machine. In some examples, the operations further include providing a feature associated with a wagering game based on the one or more characteristics of the one or more wearable computers.
US10163290B1
In one aspect, a universal receiver is provided for being operably coupled to a movable barrier operator. The universal receiver includes at least one radio antenna adapted to receive signals transmitted at different frequencies and a controller operably coupled to the at least one radio antenna. The controller is adapted to determine a code of a signal received by the at least one radio antenna at any one of the different frequencies. The controller being further adapted to learn the code in response to a user-independent learning condition being met.
US10163282B2
Systems and methods for authentication are provided. One system includes a device configured to sense electrical characteristics of an item coupled with a person and a memory storing a plurality of electrical signatures corresponding to measured electrical characteristics for a plurality of items. The system also includes a controller operable on a processor to determine if an electrical signature determined from sensed electrical characteristics of the item coupled with the person match one of the plurality of electrical signatures stored in the memory to authenticate the person having the item coupled thereto.
US10163281B2
A system and method are provided for adaptively accessing information in a vehicle under test, in a manner to avoid malfunctions associated with accessing the information. A data acquisition device is provided for accessing and retrieving diagnostic data from the vehicle. A memory unit is provided including listing of malfunctioning vehicles, as well as information associated with each of vehicle. At least one service mode request is communicated to the vehicle to identify characteristic information and characteristic features of the vehicle, which information is compared to stored vehicle characteristic information, to determine if the vehicle conforms to any of the listed vehicles, subject to malfunction. If not, additional service requests are communicated to the vehicle. If the vehicle conforms to one or more of the listed vehicles additional service request(s) are modified to remove service requests, or portions thereof, that are associated with the malfunction.
US10163269B2
Certain embodiments involve enhancing personalization of a virtual-commerce environment by identifying an augmented-reality visual of the virtual-commerce environment. For example, a system obtains a data set that indicates a plurality of augmented-reality visuals generated in a virtual-commerce environment and provided for view by a user. The system obtains data indicating a triggering user input that corresponds to a predetermined user input provideable by the user as the user views an augmented-reality visual of the plurality of augmented-reality visuals. The system obtains data indicating a user input provided by the user. The system compares the user input to the triggering user input to determine a correspondence (e.g., a similarity) between the user input and the triggering user input. The system identifies a particular augmented-reality visual of the plurality of augmented-reality visuals that is viewed by the user based on the correspondence and stores the identified augmented-reality visual.
US10163266B2
A terminal control method executed by a computer, includes detecting that an image of a reference object is included in a captured image; and sending identification information that identifies the reference object or content associated with the reference object, position information that indicates a position of the reference object or the content in the captured image, and the captured image to an information processing apparatus that is configured to combine a content associated with received identification information, with a received captured image, based on received position information.
US10163253B2
A method includes providing a three-dimensional virtual environment by executing instructions and displaying the environment in two dimensions on a display screen of a computerized appliance, defining a matrix of cells within space of the virtual environment having objects with surfaces positioned by coordinates virtual environment, determining relative occupancy values for cells intersection of objects with cells, determining in the direction of light sources, relative illumination values for the cells with consideration of intensity and direction and occupancy values, including occlusion effects from cell to cell, and displaying illumination effects on surfaces of objects by managing pixel colors and intensity according to illumination values of adjacent cells.
US10163237B2
An information display system according to the present invention includes: a graph display control unit configured to display a comparison graph in which a current transition graph representing a current period of time-series information and a previous transition graph representing a previous period of the time-series information are arranged such that time-axis components of the current period and time-axis components of the previous period which corresponds to one period before the time-axis components of the current period are placed in identical positions, in which the graph display control unit displays the previous transition graph including a portion corresponding to a future in the current period.
US10163230B2
A computer-controlled system determines attributes of a frexel, which is an area of human skin, and applies a reflectance modifying agent (RMA) at the pixel level to automatically change the appearance of human features based on one or more digital images. The change may be based on a digital image of the same frexel, for as seen in a prior digital photograph captured previously by the computer-controlled system. The system scans the frexel and uses feature recognition software to compare the person's current features in the frexel with that person's features in the digital image. It then calculates enhancements to the make the current features appear more like the features in the digital image, and it applies the RMA to the frexel to accomplish the enhancements. Or the change may be based on a digital image of another person, through the application of RMAs.
US10163229B2
A data set may be represented by samples of multiple resolutions, such as an image represented by pixels of various resolutions. When such multiple-resolution samples are potentially overlapping, it may be inefficient to render both a lower-resolution sample and also the plurality of higher-resolution samples that overlap the lower-resolution sample. Conversely, it may be more efficient to determine, before rendering a sample representing a particular data unit, whether the sample is overlapped by available higher-resolution samples that represent the same data unit. Techniques are disclosed for making this determination in an efficient manner, and for acting upon the determination to achieve improved efficiency in the rendering of the data set.
US10163224B2
For an image processing concept, a database including data derived from a plurality of frames of a video is provided in a device. A live video feed is obtained from a camera of the device. Information is extracted from an image of the video feed. A search is performed in the database using the extracted information to retrieve a list of potential frames out of the plurality of frames. An initial pose of the selected image is estimated with respect to one frame of the list as a function of the extracted information and the data derived from the one frame. Respective subsequent poses for subsequent images from the live video feed are iteratively estimated, wherein the associated subsequent pose is estimated based on said subsequent image and a respective previously estimated pose. The video feed is augmented on the device with virtual information based on the estimated initial pose and the subsequent poses.
US10163217B2
A method of locating content portion(s) of an image includes automatically determining a pixel threshold value; comparing the threshold value to the image to determine background and content sets of the pixels; determining boundaries between the background and content sets; determining the content portions using the determined boundaries; and determining bounding boxes for the content portions. A computed-radiography scanner includes an imager; a transport configured to operatively arrange a plurality of plates with respect to the imager so that a single image of the plates can be captured; and a processor configured to automatically locate the content portion(s) in the single image. A locating method includes automatically determining the pixel threshold value; determining the boundaries between portions delimited by the pixel threshold value; determining the content portions using the boundaries; and determining the bounding boxes.
US10163212B2
Various aspects of a video processing system and method are provided for object tracking in a sequence of image frames are disclosed herein. The video processing system includes one or more circuits in an electronic device that acquires the sequence of image frames, which comprises at least a current image frame and a next image frame including an object. A distribution of first pixel values in a first image space associated with a first region, which corresponds to the object in the current image frame, is determined. Based on the distribution, the current image frame is transformed to a modified current image frame that includes at least a second region that corresponds to the first region and is associated with second pixel values in a second image space. Based on one or more features extracted as a template associated with the second region, the object is tracked in the next image frame.
US10163207B2
Methods and systems for registering three-dimensional (3D) CT image data with two-dimensional (2D) fluoroscopic image data using a plurality of markers are disclosed. In the methods and systems, a lateral angle and a cranial angle are searched for and a roll angle is computed. 3D translation coordinates are also computed. The calculated roll angle and 3D translation coordinates are computed for a predetermined number of times successively. After performing the calculations, the 3D CT image data is overlaid on the 2D fluoroscopic image data based on the lateral angle, the cranial angle, the roll angle, and the 3D translation coordinates.
US10163201B2
A hardness tester includes a memory associating and storing a parts program having defined measurement conditions with respect to a sample, including a test position, and an image file acquired by capturing an image of the shape of the sample; an image acquirer acquiring image data of the sample to be measured; a pattern matcher performing a pattern matching process on the image data of the sample using the image file associated with the parts program; a determiner determining whether an image file exists which has a shape related to the image data of the sample; a retriever retrieving the parts program associated with the image file having a related shape; and a measurer measuring hardness of the sample based on the retrieved parts program.
US10163200B2
This disclosure relates to a system and method for detecting an item having at least one symmetry property inside an inspection object based on at least one transmission image. The method includes the steps: (a) detection of edges of individual items contained in the transmission image in order to produce an edge image; and (b) detection of the item by determining a symmetry line that can be associated with an item with at least one symmetry property contained in the transmission image based on pairs of edge picture elements of the edge image that are positioned symmetrically to each other relative to the symmetry line; and in step (b), in determining the symmetry line in the edge image, the only edge picture elements that are taken into account are those for which the symmetry line lies in an item contained in the transmission image, to which item the edge belongs.
US10163199B2
A recirculating aquaculture system automatically controls ammonia, bacteria, solids, and feed quantity available to a captive species in a closed, water-based habitat. Functionally Independent processing loops operate in parallel on recirculating water streams, to control each of ammonia, bacteria, solids, and feed. The same or similar components, such as an electrolytic cell, may service one or more functional loops.
US10163197B2
System and method for layer-wise training of deep neural networks (DNNs) are disclosed. In an embodiment, multiple labelled images are received at a layer of multiple layers of a DNN. Further, the labelled images are pre-processed. The pre-processed images are then transformed based on a predetermined weight matrix to obtain feature representation of the pre-processed images at the layer, the feature representation comprise feature vectors and associated labels. Furthermore, kernel similarity between the feature vectors is determined based on a predefined kernel function. Moreover, a Gaussian kernel matrix is determined based on the kernel similarity. In addition, an error function is computed based on the predetermined weight matrix and the Gaussian kernel matrix. Also, a weight matrix associated with the layer is computed based on the error function and predetermined weight matrix, thereby training the layer of the multiple layers.
US10163194B2
A non-transitory computer-readable medium encoded with a computer-readable program, which when executed by a processor, will cause a computer to execute a computational method, the computational method including collecting an image data, wherein the collecting the image data comprises collecting a first plurality of RGB images and a second plurality of hyperspectral images. The method further includes orthorectifying the image data to produce an RGB based orthophoto and a partially rectified hyperspectral orthophoto. The method further includes selecting tie features from each of the RGB based orthophoto and the partially rectified hyperspectral orthophoto. Lastly, the method includes registering the features of the partially rectified hyperspectral orthophoto into the tie features of the RGB based orthophoto.
US10163187B2
A hierarchical acceleration structure may be built for graphics processing using a 32 bit format. In one embodiment, the acceleration structure may be a k-d tree, but other acceleration structures may be used as well. 64 bit offsets are only used when 64 bit offsets are needed.
US10163180B2
This disclosure describes an adaptive memory address scanning technique that defines an address scanning pattern, to be used for a particular surface, based on one or more properties of the surface. In addition, a number, shape, and arrangement of sub-primitives of a surface to process in parallel may be determined. In one example of the disclosure, a memory accessing method for graphics processing comprises, determining, by a graphics processing unit (GPU), properties of a surface, determining, by the GPU, a memory address scanning technique based on the determined properties of the surface, and performing, by the GPU, at least one of a read or a write of data associated with the surface in a memory based on the determined memory address scanning technique.
US10163178B1
System, device, and method for enabling transit access using a multi-beam phased array antenna. One method may include repeatedly transmitting, by a location transmitter positioned within a transit location within a transit system, a location signal identifying the transit location. The method may include receiving, by a mobile communication device, the location signal, initiating a check-in process, and transmitting a device signal identifying the mobile communication device. The method may include receiving, by a gate receiver positioned within a gate within the transit location, the device signal and analyzing the received device signal to determine that a holder of the mobile communication device is entering through the gate.
US10163161B1
A graphical representation is provided that displays a user's insurance coverage via the graphical representation, the user may request information about various aspects of the coverage and/or may request to chat or speak with a representative that specializes in a particular coverage area. The graphical representation may show how the user's insurance coverage compares to population groups and medians. A user may adjust the coverage on the graphical representation and be provided with a revised premium amount. The user may select this coverage to be implemented and the user's policy may be appropriately revised.
US10163152B1
One or more computing instances are instantiated and allocated to customers. The computing instances have a modifiable interruptibility property that is operable to allow a computing instance to be terminated or reallocated from a first customer to a second customer. Requests for additional computing instances having modifiable interruptibility properties are received. Information pertaining to the instantiated computing instances and requested additional computing instances is provided. The information may include a current status of the instantiated computing instances or requested additional computing resources.
US10163150B1
Techniques for providing a seamless user experience across electronic and physical retail stores of a retailer include storing, locally with a session corresponding to a user's visit to the retailer's electronic store, indications of items that were viewed and/or focused on by the user at the electronic store. At least some of said indications may be transferred to a centralized data storage of the retailer for persistence after the session is terminated. Subsequently, an electronic device operated by the user may determine its location and determine, based on its location, a particular physical retail store of the retailer. Via communications with one or more retailer servers, items that were recently viewed by the user at the electronic store may be identified, and indications thereof may be presented on the display of the electronic device in conjunction with information corresponding to the recently viewed items at the particular physical store.
US10163142B2
A system and method for estimating a number of bags used in a purchase is disclosed. A method can comprise receiving a transmission indicating an intention by a consumer to purchase an item. Information about the item is retrieved from a database. The information about the item is associated with the consumer in a transaction. The number of bags used for the transaction is estimated. The estimation can be created using the weight and volume of a transaction. The estimation can also take into consideration the fragility, crushability, temperature-sensitivity, or cross-contamination possibility of the item. The estimated number of bags is forwarded to a mobile device. The estimated number of bags is used to determine the likelihood of unpurchased items being taken by the consumer. Other embodiments are also disclosed herein.
US10163140B2
An online merchants to third party warehouse providers broker and order fulfillment system is coupled with different third party warehouse providers that each operate one or more third party warehouses and a plurality of online merchants that use the services provided by the third party warehouse providers. The online merchants to third party warehouse providers broker and order fulfillment system includes an order fulfillment server to provide a common merchant interface to the services provided by the third party warehouse providers, a common warehouse interface to allow each of the different third party warehouse provider to communicate with the order fulfillment server in a common way including the status of the services they provide and allows each of the different third party warehouse providers to review all services requested by them, and a system operator interface to allow system operators to manage the third party warehouses including creating disaster recovery plans in case of a warehouse failure and generating a reverse invoice for each third party warehouse.
US10163132B2
A plurality of location data points is collected by a system, each location data point of the plurality of location data points corresponding to a request received at a central server from a user device of a user among a group of users. A geographic heatmap is created based on the collected plurality of location data points, the geographic heatmap identifying density distributions of the plurality of location data points, the density distributions being concentrations of the location data points included in each of a plurality of identified locations. The density distributions are analyzed within the geographic heatmap to identify a target location from one of the plurality of identified locations with a density profile including parameters exceeding one or more pre-defined thresholds. A geofence is generated around the target location, the geofence enabling detection of target users for distributions of promotional publications associated with the target location.
US10163126B2
A promotion verification method which is based upon locally stored information. The promotion verification method includes recording entry of a promotion code by a computer, determining a key from the promotion code by the computer, and applying the key to obtain promotion information associated with the promotion code by the computer.
US10163124B2
A client device detects a QR code (or NFC tag). The client device decodes the QR code. The client device determines that the data encoded within the QR code includes a URL. Based on the URL, the client device sends a first request to a first server identified by the URL. In response to the first request, the client device receives from the first server data configured to cause the client device to display, to a user of the client device, at least one of: a video or an interactive web page. Responsive to the data encoded in the QR code, the client device sends to a coupon server: identification data associated with a user of the client device, and a request for the coupon server to distribute a digital coupon for an offer associated with an identifier encoded within the QR code to an account associated with the user.
US10163121B2
Systems and methods are provided for providing targeted marketing to goods and services provides and consumer resource management services to consumers. An example system and method for targeted marketing comprises collecting transaction data from point-of-sale (POS) terminals and using a consumer identifier in the transaction data to access stored information about the consumer. This information may be used to target offers and advertisement to the consumer. In an example system for consumer resource management, a consumer may configure a consumer account on the enterprise infrastructure via a web-site. The consumer may use the consumer account to purchase and configure gift cards that may be used for purchasing goods and services. A universal transaction identifier may be associated with the consumer account and used to purchase goods and services from more than one selected goods and services providers.
US10163117B2
A system, method, and computer program product for a model-based data analysis system is disclosed. The method includes the steps of receiving information from one or more respondents that includes at least one response to a question included in a first survey, updating a model based on the received information, and generating a second survey based on the updated model. The method may be implemented by a server application communicating with a client application via a network.
US10163113B2
Implementations relate to systems and methods for generating a user profile based on periodic location fixes. A cellular telephone or other mobile device captures location information via GPS or other capability. A location history can be generated from accumulated location fixes. The location history is then analyzed to detect the user's travel and dwell patterns. That information can be combined with business classification (e.g., SIC, etc.) or Point of Interest (POI) databases to identify a user's likely home, work, or other locations based on dwell-times, time of day, and other parameters. The user's age and gender can potentially be inferred based on types of locations visited, such as school locations. The user profile can be correlated with market segmentation databases to generate a marketing rating, such as a Nielsen or Claritas rating. Advertising, media, or other content can then be tailored to the user's individual location and demographic profiles.
US10163106B2
A system and method includes an authorization request message configured with information about transaction amounts of items aggregated according to item categories and applicable rates for the items in the respective categories. Based on the information provided in the authorization request, a transaction handler is configured to compute a modified transaction amount for the transaction by reducing the transaction amount of items in one or more of the categories, without reducing the transaction amount(s) of items in one or more other categories, and computing a total transaction amount based on the reduction and the applicable rates.
US10163103B2
According to one aspect, the invention provides a system for authenticating identities of a plurality of users. In one embodiment, the system includes a first handheld device including a wireless transceiver which is configured to transmit authentication information, a second device including a wireless receiver, where the second device is configured to receive the authentication information.
US10163093B2
An information device makes a payment with a payment terminal through a contactless communication, using amount data of an electronic purse function of a mobile device. The mobile device with the electronic purse function permits the information device to be used for performing payment processing with the payment terminal, using amount data of the electronic purse function of the mobile device. A wearable information device includes an image taking unit configured to take an image of an object in the direction of line of vision of a user, and notifies the information device of the presence or absence of the information device in a taken image. The information device makes a payment with the payment terminal through a contactless communication based on the notification from the wearable information device of the presence or absence of the information device.
US10163088B2
Data structures, methods, program products and systems for creating and executing an executable file for the Binary Runtime Environment for Wireless (BREW) where the file is capable of causing presentation of a document embedded in the file on a BREW system.
US10163084B2
Aspects of the disclosure relate to deploying, configuring, and utilizing cash handling devices to provide dynamic and adaptable operating functions. A cash handling device having at least one processor, a memory, and a communication interface may store a device registration module, a containerized operating module, a non-engagement services module, and a secure communications module. The device registration module may include instructions that cause the cash handling device to register with a support server and a plurality of financial institution servers. The containerized operating module may include instructions that cause the cash handling device to selectively execute a first operating application or a second operating application. The non-engagement services module may include instructions that cause the cash handling device to generate and present one or more non-engagement user interfaces. The secure communications module may include instructions that cause the cash handling device to track and securely communicate transaction details information.
US10163081B2
A method for automatically collecting payment for a credit account includes determining if a credit account is delinquent and determining the number of days the credit account is delinquent. The method includes automatically collecting a first amount from a first account if the number of days the credit account is delinquent comprises at least a first number of days and crediting the credit account the first amount. The first account may comprise a checking account, and the first number of days may comprise twenty days.
US10163077B2
Embodiments described herein relate to enabling a lightweight way of recording and sharing video messages intended to provide input to a future meeting that cannot be personally attended. A person who cannot attend the meeting pre-records their thoughts and remarks for the meeting as video clips for presentation at the meeting. A physical device with at least a display is presented at the meeting. The physically present participants can play the pre-recorded clips on the device. Video of participants' responses to the clips is recorded and made available so that the represented attendee can view the participants' responses.
US10163070B1
A device may receive a request for a product. Based on the request, the device may determine a geographic location and delivery time for delivery of the product, and the device may identify product locations that are capable of providing the product and located near the geographic location. The device may determine, for each of the product locations and based on the product and at least one product location characteristic, a fulfillment time indicating when the product will be prepared for delivery. In addition, the device may identify at least one potential courier capable of transporting the product. Based on the fulfillment time, the delivery time, the geographic location for delivery, and at least one courier characteristic associated with the potential courier, the device may select a particular product location and a particular courier and perform an action based on the particular product location or the particular courier.
US10163064B2
A method and system for providing a connected sales associate service application via a mobile device. The application provide for an integrated platform upon which various tools for providing support to a sales associate are built. The application includes a database of information regarding the sales associates and operational information regarding a retail establishment, and provides a user interface for allowing the sales associate to access a central server for the retail establishment along with multiple additional sales associates on multiple additional mobile devices. The user interface displays information regarding trending sales data for the retail establishment and information regarding the sales associates accessing the central server. A sales associate can select and display information regarding one of the sales associates accessing the central server to at least one of view, create, delete, or assign a task to the selected sales associate.
US10163053B2
A coded tag includes a substrate. The coded tag includes a first magnetic material associated with the substrate. The first magnetic material has a first magnetic characteristic and encodes first information. The coded tag includes a second magnetic material associated with the substrate. The second magnetic material encodes second information and has a second magnetic characteristic that is different from the first magnetic characteristic.
US10163039B2
An information processing apparatus includes a set specifying unit, a clustering unit, an image selection unit, and an image arrangement unit. The set specifying unit specifies a set of images from among a plurality of images under a predetermined condition. The clustering unit classifies, after the set of images is specified by the set specifying unit, the plurality of images into any of the same number of clusters as that of image layout regions. The image selection unit collectively selects images that constitute the set of images from among the images included in the clusters generated by the clustering unit. The image arrangement unit arranges, in the image layout regions that correspond to the clusters one-to-one, the images constituting the set of images selected from the clusters by the image selection unit.
US10163036B2
One or more image parameters of an image may be analyzed using a hierarchical set of models. Executing individual models in the set of models may generate outputs from analysis of different image parameters of the image. Inputs of one or more of the models may be conditioned on a set of outputs derived from one or more preceding model in the hierarchy.
US10163032B2
An anisotropic conductive film (ACF) cutting calibration system and method are disclosed, and the system includes: a cutter, configured to cut the ACF; an image acquisition device, configured to collect a cutting mark image of the ACF according to a predetermined period; a processing device, configured to compare the cutting mark image with a predetermined image, so as to determine an offset of a cutting mark in the cutting mark image with respect to a cutting mark in the predetermined image; and a drawing device, configured to draw the ACF and adjust a speed of drawing the ACF.
US10163029B2
A camera system processes images based on image luminance data. The camera system includes an image sensor, an image pipeline, an encoder and a memory. The image sensor converts light incident upon the image sensor into raw image data. The image pipeline converts raw image data into color-space image data and calculates luminance levels of the color-space image data. The encoder can determine one or more of quantization levels, determining GOP structure or reference frame spacing for the color-space image data based on the luminance levels. The memory stores the color-space image data and the luminance levels.
US10163015B2
A system for detecting and identifying foliage includes a tracking component, a tracking parameters component, and a classification component. The tracking component is configured to detect and track one or more features within range data from one or more sensors. The tracking parameters component is configured to determine tracking parameters for each of the one or more features. The tracking parameters include a tracking age and one or more of a detection consistency and a position variability. The classification component is configured to classify a feature of the one or more features as corresponding to foliage based on the tracking parameters.
US10162996B2
Devices and methods are provided for recovering from latchup state in fingerprint sensor devices. For example, a disclosed device can be operated to perform operations that include, receiving, at a microcontroller of the fingerprint sensor device, raw sensor data from a sensor array in communication with the microcontroller, comparing the received raw sensor data against a predetermined threshold, and, based at least partly on the comparing, resetting power supplied to the fingerprint sensor device to recover from a latchup state.
US10162994B2
A capacitive fingerprint sensing apparatus includes sensing electrodes, a sensing driver and a processing module. Under a first self-capacitive sensing mode, the sensing driver combines M adjacent sensing electrodes to form a first sensing electrode set to perform a first self-capacitive sensing to obtain a first self-capacitive fingerprint sensing signal; under a second self-capacitive sensing mode, the sensing driver combines N adjacent sensing electrodes to form a second sensing electrode set to perform a second self-capacitive sensing to obtain a second self-capacitive fingerprint sensing signal. M and N are positive integers larger than 1. The processing module generates a first self-capacitive fingerprint pattern and a second self-capacitive fingerprint pattern according to first self-capacitive fingerprint sensing signal and second self-capacitive fingerprint sensing signal and combines them into a third self-capacitive fingerprint pattern. The M adjacent sensing electrodes and the N adjacent sensing electrodes share at least one sensing electrode.
US10162988B2
A radio frequency transmission method and a device thereof are provided. The method includes: transmitting a radio frequency command by a radio frequency reader; receiving the radio frequency command by a radio frequency tag, wherein the radio frequency command includes bits; determining a logic level of each of the bits based upon a time length of each of the bits at a voltage level of a voltage waveform by the radio frequency tag; and determining whether to transmit a response signal in response to the radio frequency reader based upon the logic level of each of the bits by the radio frequency tag.
US10162969B2
A system and method for analyzing cyber-security risk inter-dependencies in a control system having networked devices. The system includes a central server that has a processor and a memory device in communication with the processor. The memory device stores inter-device dependencies and quantified individual risks for each of the networked devices. The memory device also stores a dynamic quantification of risk (DQR) program. The central server is programmed to implement the DQR program. Responsive to observed cyber behavior, the central server changes one or more of the quantified individual risks to generate at least one modified quantified individual risk. The inter-device dependencies for a first of the networked devices and the quantified individual risk for at least one other of the networked devices reflecting the modified quantified individual risk are used to dynamically modify the quantified individual risk for the first device to generate an inter-device modified quantified individual risk.
US10162955B2
The present invention relates to a mobile terminal and a method for controlling the same, the mobile terminal comprising: a camera; a display unit for displaying an image inputted through the camera; and a control unit which performs a user authentication on the basis of a received first facial image when the first facial image including facial features necessary for the user authentication is received through the camera, and which performs a user authentication by using at least one facial feature included in a received second facial image when the second facial image which lacks a part of the facial features is received.
US10162953B2
A user classification apparatus and method using a keystroke pattern based on a user posture are provided. A user classification method using a keystroke pattern may include receiving keystroke data from a user, extracting feature information corresponding to a unique pattern of the user using the received keystroke data, comparing the extracted feature information to a pattern of a keystroke profile for each posture of the user pre-generated through training, and determining whether currently input keystroke data is data of a trained user based on a result of the comparing.
US10162946B2
A data management system includes a detecting apparatus that detects an information processing apparatus and a server apparatus that controls access to data by the information processing apparatus. The detecting apparatus detects the information processing apparatus located within a predetermined area. The server apparatus includes a transmitter that transfers data to the detected information processing apparatus, the data being associated with access authority indicating whether or not the information processing apparatus is allowed to access the data, and circuitry that controls an access to the data from the detected information processing apparatus in accordance with the access authority associated with the data.
US10162945B2
Various embodiments regarding an electronic device and a content providing method in an electronic device are described. An electronic device according to an embodiment comprises: a communication unit configured to transmit content and receive additional information of the content; a control unit configured to acquire information related to the secondary of the content on the basis of the additional information; and a display unit configured to display the content and the information related to the secondary of the content. Other various embodiments are also possible.
US10162939B2
Systems and methods are disclosed for identifying and modeling unresolved vessels, and the effects thereof, in image-based patient-specific hemodynamic models. One method includes: receiving, in an electronic storage medium, one or more patient-specific anatomical models representing at least a vessel of a patient; determining, using a processor, the values and characteristics of one or more patient-specific morphometric features in the one or more patient-specific anatomical models; modifying the patient-specific anatomical model using the determined patient-specific morphometric features; and outputting, one or more of, a modified patient-specific anatomical model or a patient-specific morphometric feature to an electronic storage medium or display.
US10162937B2
A method for guiding user input on a computer system of an analysis system that includes an in vitro diagnostic, IVD, device. The IVD device is coupled to the computer system that includes a display, processor, and memory to store applications being executable on the processor. A first application includes instructions that generate on the display a first graphical user interface that includes a set of user interface elements. Each user interface element is positioned in a defined region within the first graphical user interface. The first application includes instructions that control the IVD device to perform an IVD task that includes a sequence of IVD actions. The user activation of the IVD action is performed using a corresponding user interface element. The memory includes geometry data describing a display position for each interface element.
US10162929B2
The present disclosure is directed to systems and methods for using multiple libraries with different cell pre-coloring. In embodiments, the present disclosure determines a first set of cells to be placed using a single library methodology for pre-coloring and a second set of cells to be placed using a multiple library methodology for pre-coloring. In further embodiments, color-aware cell swapping can be performed based on the first set of cells and the second set of cells to align cells to swap the pre-coloring arrangements of cells to align with a track color of a closest legalization site candidate.
US10162928B2
A method for designing a semiconductor device includes establishing boundary conditions for a layout of each cell of a plurality of cells, wherein each cell has a plurality of features, and boundary conditions are established based on a proximity of each feature to a cell boundary of a corresponding cell. The method includes determining whether the layout of each cell is colorable based on a number of masks used to manufacture a layer of the semiconductor device, a minimum spacing requirement for the plurality of features, and the established boundary conditions. The method includes forming a layout of the layer of the semiconductor device by abutting a first cell of the plurality of cells with a second cell of the plurality of cells. The method includes reporting the layout of the layer of the semiconductor device as colorable without analyzing the layout of the layer of the semiconductor device.
US10162923B2
A method and system for optimizing state assignments for a finite state machine. The method generates a random initial state assignment for each of a plurality of states of the finite state machine, determines an initial cost associated with the random initial state assignments, identifies a code swap to explore as a function of a code swap probability. Further, the method calculates a cost for the code swap when one or more criteria is satisfied, updates the code swap probability as a function of the cost of the code swap and a best cost, performs the code swap when the cost of the swap is smaller than the best cost and/or a current cost to optimize the state assignments, and outputs optimized state assignments.
US10162913B2
The present invention relates to a simulation method and device. According to the present invention, a simulation method using a plurality of blocks comprises: a dividing step of dividing a simulation into computation operations for performing unique operations on the blocks and communication operations for data exchanges between different blocks; a grouping step of performing a grouping between the interdependent computation and communication operations; and a simulation performing step of performing an operation included in each group using the blocks according to whether or not the level of interdependency between the computation and communication operations is resolved.
US10162906B1
A method for creating interactive web sites that are easy to modify is disclosed. The method uses a specific web server request handler system that examines each request to determine if a handler should be called to handle information related to the referring web page. Specifically, the server system examines the address of the referring web page to see if the server has a handler routine associated with the referring web page. If the server has a handler associated with the referring web page, then the server executes the handler routine to process any information in the current request, any state information, or any other information. After executing the handler routine, the server handles the current request. The handling of the current request may be affected by the processing performed by the handler routine associated with the referring web page.
US10162900B1
Embodiments of the present disclosure are directed to methods, computer program products, computer systems for providing a computing search platform for conducting opinion searches over the Internet concerning aggregated social media electronic messages about public opinions and public sentiments for a wide variety of matrices, such as social media posting of a particular industry over a specified time period, electronic social media posting on the public sentiments, public buzz, and public mood. Methods and systems of the present disclosure are directed to collecting and analyzing unstructured social media messages and correlating with structured entity representations in order to discern amount of interest in (buzz) and feelings about (mood) the real world organizations, people, products, and locations described by those entity representations transforming the data into a readily understandable visual display of the aggregated results on a computer display.
US10162899B2
In one embodiment, a method includes receiving a query input from the first user. The method includes generating a plurality of suggested queries based at least in part on the query input, each suggested query being of a particular query-type of a plurality of query-types. Each suggested query may include one or more snippets, each snippet including contextual information about the suggested query and one or more references to the particular query-type of the suggested query. The method includes sending one or more of the suggested queries and the respective snippets for each suggested query. Each suggested query may be visually distinguished based on the particular query-type of the suggested query, and each suggested query may be selectable to execute a search query corresponding to the suggested query.
US10162895B1
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for correcting entity names. One method includes receiving texts and deriving a plurality of name-context pairs from the texts. The method further includes calculating a context consistency measure for each name-context pair and storing context-entity name data representing the name-context pairs. Another method includes identifying an entity name and one or more context terms from a query and generating candidate names for the entity name. The method further includes determining a score for each of the candidate names, selecting a number of top scoring candidate names, and using the selected candidate names to respond to the query.
US10162890B2
The present invention is directed to a search engine for a video recorder. One embodiment of the present invention operates in an environment that includes one or more set-top boxes connected to or integrated within one or more output devices. The set-top boxes are used to transfer shows from a broadcast input source to one or more types of storage devices and to play back the shows from the storage devices to the output devices, either in a delayed-live fashion or at a later time of the user's choosing. The set-top box displays a graphical user interface (GUI), which gives the user the ability to watch and/or record timeslot based programming, to order on-demand programming, and to playback previously recorded shows that reside on a local or remote storage device. A search engine is added to the GUI that lets the search for shows and receive results in an enhanced manner.
US10162888B2
Various aspects of a system and a method for accessing information associated with a sample of background audio in a computing device are disclosed herein. The computing device records, at predetermined time intervals, a sample of background audio in a vicinity of the computing device. The computing device transmits the recorded sample of background audio to a server computing device. The recorded sample of background audio and a metadata associated with the recorded sample of background audio is stored at the server computing device. The computing device accesses information associated with the recorded sample of background audio from the server computing device. The information is determined by the server computing device based on the recorded sample of background audio.
US10162886B2
In one embodiment, a method includes receiving a query including multiple n-grams; parsing the query to identify a subset of n-grams; generating, for each identified n-gram, an embedding of the n-gram; determining, for each identified n-gram, one or more word senses; calculating, for each word sense for each identified n-gram, a relatedness-score for the word sense based similarity metrics of the embedding of the word sense and the embeddings of each of the other word senses corresponding to the other identified n-grams; selecting, for each identified n-gram, one of the word senses determined for the identified n-gram having a highest relatedness-score; identifying objects matching at least a portion of the query; ranking each identified object based on a quality of matching of the object to selected word senses; and sending search results corresponding to one or more of the identified objects and having a rank greater than a threshold rank.
US10162860B2
A computer-implemented method of estimating selectivity of a query may include generating, for data stored in a database in a memory, a one-dimensional value distribution for each of a plurality of attributes of the data. A multidimensional histogram may be generated, wherein the multidimensional histogram includes the one-dimensional value distributions for the plurality of attributes of the data. The multidimensional histogram may be converted to a one-dimensional histogram by assigning each bucket of the multidimensional histogram to corresponding buckets of the one-dimensional histogram and ordering the corresponding buckets according to a space-filling curve. One or more bucket ranges of the one-dimensional histogram may be determined by mapping the query conditions on the one-dimensional histogram. The selectivity of the query may be estimated by estimating how many data values in the one or more bucket ranges will meet the query conditions.
US10162854B2
A collaborative cloud-based content curation system includes a content curation platform having a hardware processor, a memory, a master control automation unit stored in the memory, and a web-based affiliate operations portal. The hardware processor executes the master control automation unit to receive a content feed and trigger insertion instructions from an affiliate content provider, and to receive traffic log data for the affiliate content provider via the web-based affiliate operations portal. The master control automation unit curates a digital rights cleared content stream from the content feed, produces a corresponding electronic programming guide (EPG), and generates an IP transport stream for distributing the digital rights cleared content stream and the EPG. The master control automation unit also receives, after distribution of the digital rights cleared content and the EPG, a traffic log update data, and updates the EPG in real-time.
US10162839B1
A contest method and system include a sponsor displaying an advertisement accompanied by a contest invitation in association with a spectator event. A electronically geofenced perimeter of the spectator event to electronically submit affection-demonstrating digital images for contest participation, the affection-demonstrating digital images comprising at least one still image selected from a personal photograph, a family photograph, and a pet photograph portraying demonstrations of kissing, hugging, or otherwise conveying personal affection between at least two individuals or pets. Selecting a subset of the affection-demonstrating digital images from spectators located within the electronically geofenced perimeter of the spectator event as candidates for entry into a voting stage of the contest.
US10162833B2
The present disclosure provides a method of copying files at a high speed when accesses to both of a local memory physically connected to an access device and a remote memory connected via a wireless network. A file copy controller in the access device generates a FS transfer list in which logical address positions of copy sources and logical address positions of copy destinations are stored, based on file system management information of the local memory and an access list, obtained from another access device, of the remote memory, and inputs the FS transfer list to a non-volatile memory controller connected to the local memory. The non-volatile memory controller copies data between the local memory and the remote memory based on the information stored in the FS transfer list without using a CPU in the access device or an internal bus connected to the CPU.
US10162830B2
Methods, systems, and computer-readable media are disclosed for dynamic partitioning in distributed computing environments. One method includes: receiving a first data set and a second data set; mapping the first data set into a first set of key-value pairs; mapping the second data set into a second set of key-value pairs; estimating, using a sketch, a frequency count for each key based on the first set of key-value pairs and the second set of key-value pairs; determining whether the estimated frequency count for each key is greater than or equal to a predetermined threshold; and partitioning the key when the estimated frequency count for the key is greater than or equal to the predetermined threshold.
US10162825B2
In one embodiment, a geo-social networking system automatically tags one or more social contacts of a first user to a photo of the first user by ranking the social contacts based on spatial and temporal proximity to the first user, and in response to the first user's selection of one or more top ranked social contacts, associating the selected social contacts to the photo.
US10162821B2
Embodiments include a method and system for supporting a common data processing definition across multiple data processing nodes in a data swamp comprising at least one local data storage system and one or more remote data storage systems including remote databases, cloud-based data storage, or one or more computational clusters. Users can create a document in a common data processing language (e.g., XML) that describes a set of data processing tasks and a set of data processing resources to perform the data processing tasks in a graphical interface. The interface can then generate the document and send it to remote agents located in close proximity to one or more of the data processing nodes to access the necessary data and processing resources to execute the processing tasks at the appropriate node where the data and resources are located without having to migrate the data for processing.
US10162818B2
A method and apparatus are provided for processing a set of communicated signals associated with a set of muscles, such as the muscles near the larynx of the person, or any other muscles the person use to achieve a desired response. The method includes the steps of attaching a single integrated sensor, for example, near the throat of the person proximate to the larynx and detecting an electrical signal through the sensor. The method further includes the steps of extracting features from the detected electrical signal and continuously transforming them into speech sounds without the need for further modulation. The method also includes comparing the extracted features to a set of prototype features and selecting a prototype feature of the set of prototype features providing a smallest relative difference.
US10162810B2
Methods and devices are provided for inputting address information in the field of network technologies. The method includes: sending an address acquisition request to a server when an address needs to be input in a target page; receiving address information sent by the server, where the server receives the address acquisition request, acquires a geographical position of a terminal according to the address acquisition request, and determines the address information corresponding to the geographical position according to an address database; and inputting automatically the address information in an address input area of the target page.
US10162809B2
A method, non-transitory computer readable medium, and apparatus for providing a customized handwriting zone are disclosed. For example, the method receives a handwriting sample for a user, measures dimensions of the handwriting sample for the user, generates one or more handwriting zones that are sized in accordance with the dimensions of the handwriting sample of the user, receives a request to generate a form for the user and provides the form that includes the one or more handwriting zones that are customized in accordance with the dimensions of the handwriting sample of the user.
US10162808B2
A system having a processor is provided that facilitates drawing and annotation of objects on a touch screen. The processor is responsive to an object selection input corresponding to a selection of an object displayed at an object location, to display a preview type of an annotation for the selected object at an annotation location adjacent to the object location. Also, the processor stops displaying the annotation when an object deselection input is received that corresponds to a deselection of the object prior to the annotation being changed to a persistent type. Further, when the first object is selected, the processor is responsive to an annotation selection input corresponding to a selection of the annotation, to cause the annotation to change from being the preview type to being the persistent type that remains visually displayed when the object is deselected after the annotation has changed to the persistent type.
US10162805B2
Content curation can be facilitated by an application programming interface (API) for creating an address for a block of content in a document identified through a location identifier as well as APIs for retrieving content from the created address and pushing or merging the content back to the created address. Access services including conversion and merge services can be used to provide the content blocks in a suitable format for various clients. A document view is described in which a plurality of content blocks are presented as a single document even though the content blocks may be retrieved using at least two uniform resource locators (URLs).
US10162801B2
A measurement apparatus is used in cooperation with another equivalent measurement apparatus. Each measurement apparatus includes a change amount calculator for calculating a change amount of measured values, an average value generator for generating a first internal average value based on the change amount, and a communication unit for receiving a second internal average value that was generated by at least one other measurement apparatus. The average value generator generates a third internal average value, using a computation result based on at least the first and second internal average values.
US10162800B2
The present invention generally relates to systems and methods for determining the probability of a pregnancy at a selected point in time. Systems and methods of the invention employ an algorithm that has been trained on a reference set of data from a plurality of women for whom at least one of fertility-associated phenotypic traits, fertility-associated medical interventions, or pregnancy outcomes are known, in which the algorithm accounts for any woman who ceases pregnancy attempts prior to reaching a live birth outcome.
US10162793B1
Provided are systems and methods for a storage adapter device for communicating with network storage. In some implementations, the storage adapter device comprises a host interface. In these implementations, the host interface may be configured to communicate with a host device using a local bus protocol. In some implementations, the storage adapter device also includes a network interface. In these implementations, the network interface may communicate with a network using a network protocol. In some implementations, the storage adapter device may be configured to communicate with a remote storage device. In some implementations, the storage adapter device may also be configured to translate a request from the host interface from the local bus protocol to the network protocol. The storage adapter device may further be configured to transmit the translated request to the remote storage device.
US10162790B2
Disclosed is a method for clock synchronization of an industrial internet field broadband bus, wherein the method is applicable to an industrial internet field broadband bus architecture system including a bus controller and at least one bus terminal, the bus controller is connected with the bus terminal over a two-wire data transfer network, and the method includes steps of: electing one of the bus controller and the bus terminal as a best master clock; determining whether an IP address of the device of the best master clock is the same as an IP address of the bus controller; if so, then determining the bus controller as a master device of clock synchronization, and transmitting by the bus controller a synchronization message to the bus terminal for clock synchronization; and otherwise, returning to the step of electing one of the bus controller and the bus terminal as the best master clock.
US10162784B2
Examples of adapters for transmitting signals are disclosed. In one example implementation according to aspects of the present disclosure, an adapter may include a first connector communicatively couplable to PCIe port of a computing system via a first plurality of pins and a second connecter communicatively couplable to an electronic device via a second plurality of pins. The first plurality of pins is communicatively coupled to the second plurality of pins. Additionally, signals of a first type are transmittable between the computing system and the electronic device via a first subset of the first and the second pluralities of pins and signals of a second type are transmittable between the computing system and the electronic device via a second subset of the first and the second pluralities of pins. The second subset of the first plurality of pins and the second plurality of pins conforms to the SFF 8639 standard.
US10162781B2
The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses, and methods for controlling logic die circuitries. One example apparatus comprises a logic die including a first serialization/deserialization (SERDES) component and a second SERDES component coupled to the logic die, and a switch component coupled to the first SERDES component and the second SERDES component configured to activate one of the number of SERDES components.
US10162775B2
A system and method for cross-controller data storage operations comprises interconnecting a responding storage controller and an owning storage controller with a direct memory access (DMA) capable fabric, the responding storage controller and the owning storage controller each comprising an interface from a data bus connected to the DMA capable fabric, configuring and implementing a shared DMA address space in accordance with the DMA capable fabric, the shared DMA address space including memory on the responding storage controller and the owning storage controller, the shared DMA address space being one of a symmetric or asymmetric address space, and exposing one or more local buffers of the responding storage controller and one or more local buffers of the owning storage controller through the shared DMA address space.
US10162772B2
A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.
US10162761B2
An apparatus and method are described for system physical address to memory module address translation. For example, one embodiment of an apparatus comprises: a fetch circuit of a core to fetch a system physical address (SPA) translate instruction from memory; a decode circuit of the core to decode the SPA translate instruction; a first register to store an SPA associated with the SPA translate instruction; a memory controller comprising one or more channel controllers to initiate a translation using the SPA, the memory controller to transmit a translation request to a first channel controller; the first channel controller to synthesize a response including dual in-line memory module (DIMM) address information; and a second register to store the DIMM address information to be used to identify the DIMM during subsequent memory transactions.
US10162747B2
A data writing method for a rewritable non-volatile memory module is provided. The method includes: compressing data to generate first data; determining whether a data length of the first data meets a predetermined condition. The method also includes: if the data length of the first data meets the predetermined condition, writing the first data into a first physical erasing unit among a plurality of physical erasing units; if the data length of the first data does not meet the predetermined condition, generating dummy data according to a predetermined rule, padding the first data with the dummy data to generate second data and writing the second data into the first physical erasing unit. A data length of the second data meets the predetermined condition.
US10162740B1
Methods and apparatuses are described for automated intelligent execution of computer software test cases. A server computing device identifies a plurality of computer software test cases for execution using a set of input parameters. For each computer software test case, the server selects an automation testing tool from a plurality of automated testing tools based upon one or more attributes of the software test case, launches the selected automation testing tool using a tool-specific interface, executes the software test case using the automation testing tool against a software application under development, receives one or more reports from the automation testing tool that include results of the software test case execution, parses the one or more reports to determine a status of the software test case execution, and transmits the status of the software test case execution to each of a software development issue tracking system and a software deployment system.
US10162736B2
Input of a video file is received. The video file includes video of a representation of a wearable device. One or more motion vector data is determined based on the video file. One or more motion sensor data is generated based on the motion vector data. One or more test results are determined using the motion sensor data. The video file, the motion vector data, and the motion sensor data are stored.
US10162733B2
The present disclosure generally discloses a testing capability related to service testing in a communication network. The testing capability may be configured to support debugging of failures identified during service validation testing of a service in a communication network. The testing capability may be configured to support debugging of failures (e.g., transmission failures or the like) associated with a failed service validation test (e.g., a transmission verification test or the like). The testing capability may be configured to support debugging of failures identified during service validation testing of an Ethernet service. The testing capability may be configured to support debugging of failures (e.g., frame loss or the like) identified during service validation testing of an Ethernet service where the service validation testing of the Ethernet service is performed based on International Telecommunication Union (ITU)—Standardization (ITU-T) Y.1564, which is an Ethernet-based service activation test methodology.
US10162728B2
A method for monitoring the execution of a program code by a monitoring program code may include storing instructions of the program code and instructions for monitoring the program code in the same program memory. Each instruction to be monitored and the associated monitoring instructions may be simultaneously extracted from the program memory, and the instruction to be monitored and the monitoring instructions may be executed.
US10162726B2
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium are disclosed. In one aspect, a method includes filtering a first plurality of requests based on one or more criteria to generate first filtered requests, the first plurality of requests being associated with a first query plan that is associated with a first instance, identifying a first application associated with at least a portion of the first filtered requests, and determining a quantity of cores used by the first application based at least in part on the portion of the first filtered requests associated with the first application.
US10162725B1
A system, method, and computer program product are provided for providing feedback indicating an impact of user directives on a software system. In use, user input associated with a software system is received. Additionally, an impact of the user input on the software system is determined. Further, feedback is provided indicating the impact of the user input on the software system.
US10162724B2
A method for inspecting a host computer using a USB device, wherein the USB device is selectively operable in a mass storage mode and in a computing mode. The method comprises booting an inspection operating system on the host computer from the USB device, when the USB device is operated in the mass storage mode, the inspection operating system providing one or more inspection functions for inspecting the host computer, switching the USB device from the mass storage mode to the computing mode, and inspecting the host computer using the one or more inspection functions of the inspection operating system, the one or more inspection functions being controlled from the USB device operated in the computing mode.
US10162722B2
A method for replicating a virtual file system of a virtual machine. The method includes accessing a host file system usage map of a host machine that indicates active blocks out of a plurality of blocks of the host file system, and accessing a virtual file system usage map of a virtual machine that indicates active blocks out of a plurality of blocks of the virtual file system. A merged usage map is generated from information of the host file system usage map and the virtual file system usage map that identifies active blocks of the host file system associated with the virtual file system. The virtual file system is then replicated at a replication destination in accordance with the merged usage map.
US10162718B2
Methods and systems for tracking information that is transferred from a source to a destination storage system are provided. The source storage system maintains a first data structure for indicating that a storage block has been transferred. The destination storage system receives the storage block and updates a second data structure to indicate that the storage block has been received. The first data structure and the second data structure are compared to determine that the storage block was successfully transferred from the source storage system and received by the destination storage system.
US10162709B1
Techniques for storing incremental backups in long-term storage are described herein. A backup data set is generated from a set of data to backup and a deletion time for that backup data set is determined. A scheduled time period to perform the backup is selected based at least in part on a requested time period to perform the backup. The requested time period is altered if the performing the backup at the requested time period would produce a period of high resource contention at the destination for the backup. The backup is then stored at the destination at the scheduled time.
US10162707B2
An electronic device including a memory storing an application program that provides a guide about a user action, collects information on a performance of the user action, or collects information on a user state. A processor connected to the memory is configured to execute the application program, to detect a cause by which the application program is stopped, and to automatically reexecute the application program or to provide a user interface for receiving a user input for the reexecution of the application program on the basis of at least a portion of the detected cause.
US10162702B2
In one embodiment, memory circuitry includes an error-correction code (ECC) encoder, memory, and an ECC decoder. The ECC encoder performs encoding, based on an ECC algorithm having an algorithm size, on an algorithm-size segment of input user data to generate a corresponding subset of parity data for the segment of input user data. The memory has input user data and corresponding parity data written based on a write data size and stored user data and corresponding stored parity data read based on a read data size. The ECC decoder performs decoding, based on the ECC algorithm, on an algorithm-size segment of retrieved user data and a corresponding subset of retrieved parity data, wherein the algorithm size is smaller than the write data size or the read data size. The memory circuitry enables conventional SEC-DED algorithms to be used when the write and read data sizes are different.
US10162695B2
An information processing apparatus and a fault diagnosis method for monitoring signals relating to the start of a CPU to determine that a failure occurs, in a case where a predetermined signal is not output within a predetermined time period after the output of a predetermined signal, and determine the failure type based on the signal states at the time of the occurrence of the failure to display information corresponding to the failure type.
US10162694B2
Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.
US10162693B1
A method of troubleshooting a mobile device receiving at a diagnostic server an initial snapshot of characteristics from a mobile device, wherein the initial snapshot includes metrics that will identify the mobile device, elements that will expose a performance issue related to the mobile device, and metrics that enable determination of a corrective action for remedying the performance issues, determining with a diagnostic processor the performance issue based on the initial snapshot, receiving at an evaluating server an after-care snapshot of the characteristics from the mobile device after a corrective action has been performed on the mobile device, and determining with an evaluating processor whether the corrective action remedied the performance issue based on the after-care snapshot.
US10162689B2
The disclosed embodiments relate to regulation of receipt, rate or volume, and processing of messages, such as order, mass quote or other trade related messages by available trading system resources to minimize congestion, maximize efficient use, minimize unfair monopolization and ensure fair access to/allocation thereof. The disclosed embodiments may act as a governor limiting the maximum rate of message submission to the rate at which the submitted messages can be processed. In particular, the number of concurrent, i.e. received/accepted but not yet completed/processed/responded to, messages may be limited. As long as the limit is not exceeded, i.e. the rate of completion/processing meets or exceeds the receipt rate, no interruption may be imposed. However, once the limit is reached, subsequently received messages may be buffered or otherwise dropped. In this way, the limit may define the extent to which incoming messages may consume the concurrent processing capacity, or allocated portion thereof.
US10162676B2
A content of a social media data is analyzed. The social media data relates to a workload that is to be located on a node. A location corresponding to the social media data is computed. The social media data is regarded as originating from the location. A set of nodes is selected by computing a social distance objective function, the set of nodes includes the node. Each node in the set of nodes is located within a range of distances specified by the social distance objective function. A first subset of nodes is removed from the set of nodes, where the first subset of nodes fails to satisfy another objective function. In response to a second subset of nodes satisfying the social distance objective function and the other objective function, the node is selected from the second subset and the workload is deployed on the node.
US10162665B1
A memory management module receives a request to access a page in a memory, sends the request to a memory controller controlling the memory if the page is available in the memory, and if the page is unavailable, (i) does not send the request to the memory controller, and (ii) generates a first exception. A hypervisor intercepts the first exception and sends a second exception to an operating system. The operating system includes a handler to, in response to the second exception, selectively request the memory controller to obtain the page from a storage device into the memory, and to suspend execution of a first thread issuing the request on a processor until the page becomes available in the memory; and a kernel to schedule execution of a second thread on the processor until the page becomes available, or to idle the processor until the page becomes available.
US10162653B2
A management agent operates transparently in the background on each endpoint computing device that needs to be managed. The agent sets up a sandboxed environment on the endpoint computing device on which it is operating in order to capture applications that have been installed on the endpoint device. The application capture is performed after the applications have been installed on the endpoint device and therefore does not require installing the application on any dedicated staging machine, nor any recording of the pre-installation state. The application capture process involves running the application from an isolated sandboxed environment on the computing device in order to identify all necessary components of the application by monitoring accesses by the application to components located outside of the sandbox. The identified components can then be packaged together and managed as individual application packages.
US10162650B2
Techniques are presented for managing a deployment pipeline using an inheritable and extensible source code template—generally referred to as a live pipeline template (LPT). As described, live pipeline templates may be used to manage deployment pipelines which, in turn, are used to launch, maintain, and update the services and systems used to host and provide computing services.
US10162646B2
A system includes a programmable non-volatile memory, a switch, a control chipset, and a basic input/output (BIOS) module. The switch has a first terminal coupled to the programmable non-volatile memory, and a second terminal coupled to the control chipset. The control chipset is configured to store a SKU parameter set in the programmable non-volatile memory according to a predetermined memory allocation. The BIOS module is coupled to the control chipset, and is configured to load and update the SKU parameter set according to the predetermined memory configuration during a booting operation of the motherboard.
US10162640B2
A processor is described having a functional unit within an instruction execution pipeline. The functional unit having circuitry to determine whether substantive data from a larger source data size will fit within a smaller data size that the substantive data is to flow to.
US10162636B2
A control apparatus, an integrated circuit, and a management method for a stack are provided. The management method for the stack includes: obtaining an instruction of running a task with a first function; changing a pointer of the stack in an internal memory from pointing to an internal memory to an external memory before executing the first function, wherein the stack in the internal memory is used by the task; executing the first function, wherein first temporary information that is needed to be stored during a period of executing the first function is stored into the external memory pointed to by the pointer of stack; and adjusting the pointer of the stack to point to the internal memory after finishing executing the first function. According to the above-mentioned management method for the stack, the cost is reduced, and low power consumption can be achieved.
US10162635B2
An apparatus includes a network interface, memory, and a processor. The processor is coupled with the network interface and memory. The processor is configured to determine that an instruction instance is a branch instruction instance. Responsive to a determination that an instruction instance is a branch instruction instance, the processor is configured to obtain a branch prediction for the branch instruction instance and a confidence value of the branch prediction. The processor is further configured to determine that the confidence for the branch prediction is low based on the confidence value, and responsive to such a determination, generate predicated instruction instances based on the branch instruction instance.
US10162628B2
A data analysis and transformation engine provides a service that automatically analyzes, formats, and/or reviews changes made to collection of artifacts stored in one or more source control systems in accordance with a user's instructions in a coordinated manner. A user subscribes to the data analysis and transformation engine with instructions on the user's preference for formatting, reviewing, and analyzing an artifact after the artifact was modified and checked into a source control system.
US10162626B2
Technologies that allow for a significant reduction in the time required to incrementally build large computer programs, and increase in the scale of build systems that perform builds. The time reduction is caused by reducing the time required for processing systems in a distributed build system to acquire files needed for the respective processing system to perform their respective part of the build. The scale increase comes from relying on local processing systems instead of centralized processing systems. This is done by establishing a tier of cache locations on which appropriate files for a build may be found by the appropriate processing system. A system may be established that allows for the processor systems to validate that the files have not been tampered with by using signatures, and were appropriately identified.
US10162617B2
Systems and methods for binary translation are disclosed. In some implementations, guest software to run in a Native Client environment is received. The guest software is configured to execute at a specified guest hardware architecture and not within the Native Client environment. A binary translation of the guest software into Native Client compatible machine code is provided using emulation software. The Native Client compatible machine code executes within a sandbox for the Native Client environment. The Native Client compatible machine code is executable within an application. Providing the binary translation of the guest software into the Native Client compatible machine code for execution within the sandbox occurs just in time, during a runtime of the emulated guest software, and without porting or recompiling the guest software. Providing the binary translation interleaves with execution of the emulated guest software.
US10162611B2
A method and apparatus for migration of application source code may include parsing the source code and generating a first output, dynamically analyzing the source code to produce a second output wherein the second output comprises at least business rule metadata associated with the application, converting, using the at least business rule metadata, the source code of the application in an original language to a destination language on the second platform and a data source in an assigned format to a destination format. The method may include simulating memory to execute the source code by creating a dynamic memory array, executing the source code within the dynamic memory array, detecting and resolving parameters of the source code by monitoring execution of the source code, and storing the detected and resolved parameters of the source code in a metadata register.
US10162602B2
The invention relates to methods for handling user-level events for programming an application. The methods aim at providing the designer of an application the ability to use easily understandable user-level events rather than low-level, often platform dependant input events, whose use generally requires important programming skills. It also aims at optimizing the generation of user-level events, by improving the detection of events and detecting only a subset of possible user-level events depending on the context of the application.
US10162590B2
The system is comprised of a hub which in turn is made of a housing, at least one video input port, at least two video output ports, a digital card enabling communication between a computer and at least one display without a direct physical connection and a processor. The hub is used to make a video wall.
US10162582B2
The present invention provides a method for recording chip usage state information, a chip of imaging cartridge and an imaging cartridge. The chip of imaging cartridge includes: a substrate, and an information storage unit and a control unit which are provided on the substrate, the information storage unit includes a prioritized writing area and a normal read-write area, the method includes: when the chip receives a read/write operation command sent by an imaging device or when the control unit on the chip monitors a communication interference signal, the control unit on the chip updates a chip service state parameter stored in the prioritized writing area, the chip service state parameter is used for fault analysis of the chip. The chip service state parameter recorded can represent the usage state information of the chip itself, which provides powerful information to find and solve communication problems between the chip and the imaging device.
US10162581B2
An information processing apparatus includes a receiving unit and a controller. The receiving unit receives an access request from another apparatus. If an IP address of the own apparatus is a global IP address, the controller makes no response to or reject the access request unless a predetermined condition indicating that the other apparatus belongs to an organization to which the own apparatus belongs is satisfied.
US10162574B2
A storage control device that includes processing circuitry that receives second access instructions of a plurality of series generated based on a first access instruction for instructing writing of data in a first storage or reading of data from the first storage, through a plurality of channels, the storage control device being connected to a controller configured to perform writing of data in the first storage or reading of data from the first storage according to an instruction for accessing the first storage, reassembles the first access instruction based on the second access instructions of the plurality of series received by the processing circuitry, and outputs the first access instruction reassembled by the processing circuitry to the controller.
US10162565B2
Examples herein disclose erasing data from a target device based upon an authentication of an erase command. The examples receive an erase command during execution to boot strap information and authenticate the erase command. Upon the authentication of the erase command, the examples erase data from the target device prior to completion of execution of boot strap information.
US10162560B2
A memory unit, which has a plurality of memory locations for accommodating data and which is designed to copy the content of a first memory location of the memory unit, when this first memory location is written, automatically into a first memory location at least of one other memory unit, the first memory location of the at least one other memory unit being readable and writable independently of the first memory location of the memory unit; and to a data network having at least two such memory units, a transmitter and at least one receiver, the transmitter being designed to write a datum to be sent into the first memory location of a first of the at least two memory units, and the at least one receiver being designed to read and to process the datum from the first memory location of a second memory unit of the at least two memory units.
US10162555B2
Deduplicating snapshot associated with a backup operation is disclosed, including: performing a backup operation including by generating a plurality of snapshots; maintaining, at a source system, deduplication data corresponding to one or more data blocks that have already been written to backup media during the backup operation; and using the deduplication data to deduplicate backup data across the plurality of snapshots.
US10162553B2
In one aspect, the present disclosure relates to a method of de-duplicating data in a solid state storage device. The method can include receiving a block of data to be written to a solid state storage device, wherein the block of data comprises header portion and a payload, wherein the header portion comprises context information; and determining whether the payload should be de-duplicated prior to storage, based on the context information stored within the header portion; if the payload is determined to be de-duplicated, de-duplicating the payload; and storing the de-duplicated payload to the solid state storage device.
US10162547B1
Aspects of the disclosure provide a method for linking input files during a linking process. The method includes receiving an input section that is to be mapped to a memory segment by a linker circuit, determining whether an out-of-memory (OOM) event occurs when an available memory space of the memory segment is unable to accommodate the input section, estimating a memory expansion size that would be required for the memory segment to be able to accommodate the input section when an OOM event occurs, and creating by the linker circuit a map file that includes the estimated memory expansion size of the memory segment.
US10162539B2
An information processing apparatus includes circuitry that controls mounting or unmounting of a specified storage area to an operating system on the information processing apparatus and a memory that stores a first mount status indicating whether or not mounting or unmounting operation is performed to the information processing apparatus and a second mount status indicating whether or not the specified storage area is mounted. The circuitry presents the specified storage area as an available mounted storage area to a user if the second mount status indicates that the specified storage area is mounted, and does not present the specified storage area as the available storage area if the second mount status indicates that the storage area is not mounted.
US10162534B1
Systems and methods for utilization of notification or ordering commands are disclosed that can enable more efficient processing of flush requests from software programs and increase data consistency in storage devices. A data storage device or system may include a non-volatile memory, a memory comprising a data cache and a controller. The controller may be configured to receive an ordering command requesting commitment to the non-volatile memory of cached data items associated with a first identifier prior to commitment of cached data items associated with a second identifier, and to delay commitment of the second data item to the non-volatile memory until commitment of the first data item to the non-volatile memory, based at least in part on the ordering command. The controller may be further configured to select data items from the data cache for commitment to the non-volatile memory in accordance with native command queuing (NCQ).
US10162532B2
A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.
US10162531B2
A method for optimizing the allocation of extents to data sets is disclosed. In one embodiment, such a method includes providing multiple storage classes. These storage classes may include a first storage class configured to allocate larger extents to data sets, a second storage class configured to allocate smaller extents to data sets, and a mixed-mode storage class configured to allocate a combination of the smaller and larger extents to data sets. The method further enables data sets to be assigned to one of the multiple storage classes. Upon assigning a data set to the mixed-mode storage class, the method causes an initial portion of the data set to be allocated the larger extents, and an ending portion of the data set to be allocated the smaller extents. A corresponding system and computer program product are also disclosed.
US10162524B2
A method for execution by a computing device of a dispersed storage network (DSN). The method begins by receiving a data segment of a data object for dispersed storage error encoding. Prior to the dispersed storage error encoding, the method continues by determining whether to compress the data segment by predicting a first estimated processing cost based on estimated processing costs to compress the data segment to produce a compressed data segment and estimated processing costs to dispersed storage error encode the compressed data segment and predicting a second estimated processing cost based on estimated processing costs to dispersed storage error encode the data segment. When the first estimated processing cost compares favorably to the second estimated processing cost, the method continues by compressing the data segment to produce the compressed data segment and dispersed storage error encoding the compressed data segment to produce a set of encoded data slices.
US10162518B2
Systems, methods, and software are disclosed herein for supporting reversible ink in a user interface to an application. In an implementation, an application receives inking input on a canvas in a user interface to the application. The application renders ink on the canvas along a path taken by the inking input and monitors for the inking input to reverse direction along the path. In response to the inking input reversing the direction along the path, the application erases at least a portion of the ink from the canvas.
US10162517B2
Techniques for cross-application content item management. In one embodiment, for example, a method comprises detecting a touch gesture related to a representation of a content item displayed by a first application. And based at least in part on detecting the touch gesture, a different application performing a content management action on the content item. The content management action may encompass storing the content item in a content item collection, sharing the content item with a user account, uploading the content item to a server, or a combination thereof.
US10162515B2
The present disclosure discloses an information processing method and an electronic device. The method comprises: detecting and acquiring a first touch operation on a touch display unit of the electronic device when M display objects are displayed on the touch display unit, wherein M is an integer greater than or equal to 1; and controlling N of the M display objects to be in a selected state in response to the first touch operation, and generating and executing a first operation instruction for implementing a first operation on the N display objects, wherein N is a positive integer less than or equal to M.
US10162508B2
The present disclosure provides a portable terminal and a method for managing content stored in a plurality of devices. The method includes displaying information associated with a plurality of electronic devices registered under a user identifier; searching content items stored across the plurality of electronic devices; and displaying content items found across the plurality of electronic devices.
US10162502B2
Animation for the attachment of content items to a location on a content surface in a user interface is provided. A user interface showing a content surface may be displayed on a computer. The content surface may include a content item at an initial position above the content surface. The content surface may display content formatted for display over an area comprising a totality of the content surface. The computer may then receive in the user interface a request to attach the content item to a final position on the content surface. The computer may then display an animation of the content item moving, from the initial position, across the content surface until the final position has been reached. The computer may then attach the content item to the content surface at the final position.
US10162494B2
An electronic device including a touch-enabled display module configured to display a plurality of windows according to a multi-window mode; and a control module configured to displaying on the touch screen a first application window and a second application window according to the multi-window mode, alter the first application window in response to a touchscreen input received via the touch-enabled display, and automatically alter the second application window in response to the alteration of the first application window.
US10162490B2
A method for displaying transmission status of a multimedia messaging service (MMS) message and a telecommunication terminal using the method, including displaying the currently transmitting content and transmission progress of the MMS message while the telecommunication terminal transmits the MMS message. A user can check the content of the MMS message being currently transmitted together with the transmission progress of the MMS message. The user also can cancel the transmission of the erroneous MMS message before completing the transmission of the MMS message.
US10162487B2
This disclosure relates to adaptive content control and display for internet media. A playback component provides for playback of media content. An input component detects user inputs during playback of the content. In response to the user inputs being detected, a menu component displays a level of a pivot menu during playback of the content. The pivot menu is displayed on top, or in front, of a portion of the content during playback, and the pivot menu can be at least partially transparent to enable consumption of the content to continue without complete obstruction.
US10162484B2
A first accepting unit (111) of an exemplary server device (100) accepts from a user an instruction to select one of plural selection targets. A user selecting unit (112) selects, from among plural users other than the user, another user who has recommended or evaluated the selection target, selection of which has been accepted by the first accepting unit (111). A selection target selecting unit (113) selects one or more selection targets that the other user selected by the user selecting unit (112) has recommended or evaluated. A presenting unit (114) presents, to the user, information on the one or more selection targets selected by the selection target selecting unit (113).
US10162483B1
Systems and methods for providing user interfaces are disclosed. In certain embodiments, a menu having a number of icons can be provided on a display device such that the icons are arranged around an initial cursor position, or an area that is touched by a user's finger or stylus, for example. Due to the icons being arranged around the initial cursor position, any one of the icons from the menu can be chosen with relatively small cursor movement. In certain embodiments, the menu can be divided into regions that overlap with the icons, such that cursor movement from the initial cursor position into a given region has a similar effect as movement into the corresponding icon itself (without actually moving the cursor onto the desired icon).
US10162481B2
Disclosed herein are methods for creating a food or drink recipe and systems for implementing the same. Ingredients in the food or drink recipe are combined to create a desired characteristic of the end food or drink product. Some or all of the ingredients can be subject to one or more methods of preparation. The ingredients are selected based on compatibility between pairs of ingredients.
US10162477B2
A system for personalized navigation of computer screens. The system can comprise electronic data processors. The system can also include a module configured to execute on the electronic data processors, where the module can be configured to display a plurality of icons retained in a file associated with a particular user on a computer screen. The icons can comprise one or more assigned icons from an assigned icons list and candidate icons from a candidate icons list, where both the assigned and candidate icons are derived from a pool of icons. Also, the module can be configured to assign an icon to a currently displayed screen by utilizing a selection tool and placing the icon in the assigned icons list, where the icon is selected from the candidate icons list. The module can be further configured to return to the assigned screen when the assigned icon is selected.