US10855358B2
This application provides a channel state information feedback method and an apparatus. The method includes: generating first frequency domain indication information and M1 pieces of first precoding indication information, where the first frequency domain indication information is used to indicate L1 frequency domain subbands in T frequency domain subbands, the T frequency domain subbands are a system bandwidth or a part of the system bandwidth, 1≤L1
US10855351B1
A wireless device includes a radio, a first directional antenna, a second directional antenna, an omnidirectional antenna, and a switch selectively coupled between the radio and the first directional antenna, the second directional antenna, and the omnidirectional antenna. A processor is coupled to the switch and to, for a frame: determine, based on an arbitration table, a destination medium access control address of a client wireless device and identifiers of antennas for transmitting the frame and receiving acknowledgement data; cause the switch to couple the radio to the first directional antenna; transmit the frame to the client wireless device via the first directional antenna, wherein the first client wireless device is located along a first direction with respect to the wireless device; cause the switch to couple the radio to the omnidirectional antenna; and receive an acknowledgment, corresponding to the frame, from the client wireless device via the omnidirectional antenna.
US10855347B2
A base station according to this disclosure includes a plurality of antennas used for transmission and reception, an adaptive array processing unit that performs adaptive array processing on reception signals received by the plurality of antennas, and a control unit that decides a transmission antenna used for the transmission from the plurality of antennas at a time when a transmission signal is transmitted, and the control unit decides the transmission antenna based on transmission weight vectors respectively corresponding to the plurality of antennas obtained from a processing result of the adaptive array processing unit.
US10855338B2
A distributed antenna system (DAS) includes: a base station network interface; and a remote antenna unit communicatively coupled to the first base station interface, the remote antenna unit including an antenna. The remote antenna unit configured to: receive a radio frequency band signal from a subscriber unit; convert the radio frequency band signal into a data stream; and communicate the data stream with the first base station network interface. The first base station network interface is configured to: convert the data stream or a signal derived from the data stream into a communication signal, wherein a mater reference clock is distributed between various components of the DAS to keep the various components of the DAS locked to a single clock; and communicate the communication signal and the master reference clock to an external device, the external device configured to lock its clock to the master reference clock.
US10855329B2
A hopping spread-spectrum wireless network for IoT applications with mobile device that have unsynchronized local frequency references. The transmitters use hopping sequences defined in term of the relative differences of frequencies, in such a manner that a receiver can determine the hopping sequence of a transmission despite the presence of a large frequency error.
US10855328B1
Methods, systems, computer-readable media, and apparatuses for transmitting and receiving radar signals from a radar source while minimizing interference with other radar sources are presented. A transmit signal comprising a first chirp sequence is generated according to a set of waveform parameters, with least one waveform parameter being varied for one or more chirps in the first chirp sequence. Additionally, each chirp of the first chirp sequence can be phase-modulated. A receive signal comprising a second chirp sequence and corresponding to the transmit signal reflected off an object in a surrounding environment is then sampled to determine one or more attributes of the object. In some embodiments, the attributes include distance and speed values calculated using Discrete Fourier Transforms (DFTs). Other attributes that can be calculated from the receive signal include azimuth angle and elevation angle.
US10855327B2
The disclosed systems, structures, and methods are directed to a wireless receiver. The configurations presented herein employ a signal encoding module to encode a plurality of received analog signals with an orthogonal code set and combine the encoded analog signals into a single encoded analog composite signal, an analog-to-digital conversion unit to convert the single encoded analog composite signal into a single encoded digital composite signal containing constituent digital signals. The presented configurations also include a bank of multiple successive interference cancellation (SiC) modules to sequentially remove the constituent digital signals from the single encoded digital composite signal until a single constituent digital signal remains and a decoding module configured to decode the remaining constituent digital signal from the single encoded digital composite signal.
US10855322B2
An information handling system transceiver adjusts power levels for transmitting wireless signals to maintain specific absorption constraints by estimating the type of material proximate an antenna and applying the estimated material to adjust transmit power levels. When the capacitive response of an object in proximity to the antenna indicates an inanimate object, such as a desktop surface or a portion of a housing, the power level may be maintained at a high setting and remain within specific absorption constraints.
US10855317B2
An RF receiver includes a low-noise amplifier (LNA) to receive and amplify RF signals, a transformer-based IQ generator circuit, one or more load resisters, one or more mixer circuit, and a downconverter. The transformer-based IQ generator is to generate a differential in-phase local oscillator (LOI) signal and a differential quadrature (LOQ) signal based on a local oscillator (LO) signal received from an LO. The load resisters are coupled to an output of the transformer-based IQ generator. Each of the load resisters is to couple one of the differential LOI and LOQ signals to a predetermined bias voltage. The mixers are coupled to the LNA and the transformer-based IQ generator to receive and mix the RF signals amplified by the LNA with the differential LOI and LOQ signals to generate an in-phase RF (RFI) signal and a quadrature RF (RFQ) signal. The downconverter is to down convert the RFI signal and the RFQ signal into IF signals.
US10855315B2
Techniques are described for wireless communication. One method includes segmenting a payload into a plurality of code blocks; generating, for each code block, a cyclic redundancy check (CRC); encoding each code block and associated CRC in one or more codewords of a plurality of codewords; and transmitting the codewords. The encoding is based at least in part on a low density parity check code (LDPCC) encoding type. Another method includes receiving a plurality of codewords associated with a payload encoded using a LDPCC encoding type; decoding a set of the codewords associated with the first payload and a CRC; and transmitting one of an acknowledgement (ACK) or a non-acknowledgement (NAK) for the set of the codewords.
US10855311B2
A method for determining features of an error correcting code system, comprising independent error correcting codes and a polarization module, allowing transmitting a binary input vector on block fading sub-channels, the independent error correcting codes generating components of the binary input vector and a channel polarization being applied to the binary input vector by the polarization module. The method comprises: obtaining characteristics of the block fading sub-channels; and, determining features of said error correcting code system, comprising, for each error correcting code, a rate of said error correcting code, adapted to the obtained characteristics and minimizing a function of a probability that an instantaneous equivalent channel capacity of the block fading sub-channels is below a transmission rate transmitted on the block fading sub-channels.
US10855308B2
Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.
US10855306B2
A digital-to-analog converter (DAC) capable of operating in radio frequency (RF) with linear output, low distortion, low power consumption, and input data independence. The DAC includes switch drivers and output switches driven by the switch drivers. The switch drivers include pairs of outputs, and positive feedback circuitries coupled between respective pairs of outputs. The output switches are arranged between a first current source configured to push current to the DAC's outputs and a second current source configured to pull current from the DAC's outputs. Different output switches are configured to push current to and pull current from the DAC's outputs in accordance with rising edges and falling edges, respectively.
US10855303B1
Various embodiments provide a filter for propagation delay compensation and interpolation in encoder digital signal processing. The filter can include a first low pass filter configured to reduce noise of a digital input comprising a measured angular position; a first differentiator configured to receive a filtered digital input and to calculate a speed from a difference in time of the measured angular position and a previous angular position; a second low pass filter configured to reduce noise from the speed; a second differentiator configured to receive a filtered speed and to calculate acceleration using a difference in time of the filtered speed and a previous speed; a third low pass filter configured to reduce noise of the acceleration; and a delay compensator configured to receive the filtered digit input, the filtered speed, and a filtered acceleration, and to calculate a propagation delay compensated digital output.
US10855302B2
Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC.
US10855301B2
A digital-to-analog converter (DAC) device includes a DAC circuitry and a calibration circuitry. The DAC circuitry includes first and second DAC circuits which generate first and second signals according to an input pattern. The input pattern includes at least one of first logic value and at least one of second logic value that have different numbers. The calibration circuitry performs a calibration operation according to first and second comparison results, to generate a control signal for controlling the second DAC circuit. The first comparison results are comparison results of the first and the second signals when the input pattern is a first pattern, the second comparison results are comparison results of the first and the second signals when the input pattern is a second pattern, and the first pattern is inverse to the second pattern.
US10855299B2
Described herein are DACs with low distortion for high dynamic range (HDR), extremely high dynamic range (EHDR), and other suitable applications. Some embodiments relate to a device including a DAC configured for coupling to an amplifier via a force path and a sense path. For example, the DAC may provide output current to the amplifier via the force path, and the DAC may sense the input voltage of the amplifier via the sense path. Accordingly, distortion such as harmonic distortion and/or gain offset from parasitic impedances in the force and/or sense paths may be reduced or eliminated. Some embodiments relate to a DAC including a voltage reference generator configured to compensate for variations in impedances of the DAC, such as due to semiconductor process variation. Accordingly, distortion in the DAC output due to variations in the DAC impedances may be reduced or eliminated.
US10855296B2
A circuit for calibrating an injection locked oscillator is provided. The injection locked oscillator includes an injection locking input, an LC tank and an oscillator output to output an oscillator output signal. The circuit is configured to adjust a capacitance of the LC tank to different values, detect an amplitude of the oscillator output signal for each value of the different values of the capacitance while an input signal having a target frequency is applied to the injection locking input, determine a maximum amplitude of the detected amplitudes, and select a value for operating the injection locked oscillator based on the determined maximum amplitude.
US10855295B2
Methods, systems, and devices for section-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include selecting at least one of the sections for a voltage adjustment operation based on a determined value of a timer, and performing the voltage adjustment operation on the selected section by activating each of a plurality of word lines of the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.
US10855294B2
A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.
US10855293B2
The present disclosure discloses a quick-start clock system, which includes: a digital subsidiary circuit configured to output a digital control value; a phase-locked loop including a programmable voltage-controlled oscillator circuit and a frequency dividing circuit connected to each other and both connected to the digital subsidiary circuit, the programmable voltage-controlled oscillator circuit obtains the digital control value output, and output a clock signal according to the digital control value, the frequency dividing circuit performs a frequency dividing operation on the clock signal; and a crystal oscillator circuit connected to the phase-locked loop, which includes a crystal and an oscillation injecting circuit connected to the crystal, the oscillation injecting circuit converts the clock signal performed with the frequency dividing operation to a co-frequency fully differential signal, and inject the co-frequency fully differential signal into the crystal.
US10855284B1
A method of routing interconnects of a field programmable gate array including: a plurality of logic tiles, and a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects to interconnect logic tile networks of the logic tiles, the method comprises: routing a first plurality of tile-to-tile interconnects in a first plurality of logic tiles. After routing the first plurality of tile-to-tile interconnects, routing a second plurality of tile-to-tile interconnects in a second plurality of logic tiles. The start/end point of each tile-to-tile interconnect in the first plurality and the second plurality of tiles is independent of the start/end point of the other tile-to-tile interconnects in the first and second plurality, respectively. Routing the second plurality of tile-to-tile interconnects includes connecting at least one start/end point of each tile-to-tile interconnect in the second plurality of tiles to at least one start/end point of each interconnect in the first plurality of tiles.
US10855280B2
A circuit receives an input signal that switches between reference and first voltage levels, a power node carries a second voltage level, and a set of transistors is coupled between the power node and an output node. The second voltage level is a multiple of the first voltage level, and the multiple and a number of the transistors have a same value greater than two. A control signal circuit includes a level shifting circuit including a series of capacitive devices paired with latch circuits, a number of the pairs being one less than the value of the multiple, and, responsive to the input signal, outputs a control signal to a gate of a transistor of the first set of transistors closest to the power node, the control signal switching between the second voltage level and a third voltage level equal to the second voltage level minus the first voltage level.
US10855278B1
Modular layout design units are provided with an internal channel for multi-directional distribution of a shared signal. In one illustrative embodiment, an integrated circuit includes: one or more modular units, each modular unit having an internal channel for signal distribution. The internal channel possesses: an edge connection on each edge of the modular unit; a hub node coupled to each edge connection by a respective bi-directional buffer having an incoming buffer and an outgoing buffer with at least one of the incoming and outgoing buffers disabled, the bi-directional buffers cooperating to steer a signal from a selectable one of the edge connections to one or more of the other edge connections; and a tap providing the signal for use by internal circuitry of the modular unit.
US10855272B1
A gate drive apparatus is provided. The gate drive apparatus includes a gate drive unit configured to drive a gate of a switching device; a parameter measuring unit configured to measure a parameter corresponding to current flowing through the switching device; a discrepancy detection unit configured to detect discrepancy between current flowing through the switching device during an on-state of the switching device and a reference value, based on the parameter; and a control unit that, if the discrepancy is not detected, switches a change speed of a gate voltage of the switching device at a timing when a reference time has elapsed since a turn-off start of the switching device during a next turn-off time period of the switching device, and if the discrepancy is detected, keeps the change speed of the gate voltage during the next turn-off time period of the switching device.
US10855271B2
In a control device that drives a semiconductor switch element, a first control switch is connected between a signal line and a source terminal or an emitter terminal of a semiconductor switch element. The signal line supplies a driving signal to a gate terminal or a base terminal of semiconductor switch element. The first control switch is controlled to an ON state when the semiconductor switch element is controlled to an OFF state. A second control switch is connected between the signal line and the source terminal or the emitter terminal in parallel with the first control switch. The second control switch is turned on when a potential of the source terminal or the emitter terminal becomes a negative potential.
US10855264B1
A circuit for generating differential reference voltages, a circuit for detecting a signal peak, and an electronic device. In the circuit for generating reference voltages, a common-mode extraction circuit receives a first differential signal and a second differential signal, extracts a common-mode level from the first differential signal and the second differential signal, and applies the common-mode level to a non-inverting input terminal of a first operational amplifier. The first operational amplifier, a main control switch, a first voltage dividing resistor, a second voltage dividing resistor, and a first direct current power source constitute a feedback loop, to generate differential reference voltages matching with the common-mode level. Adjusting a current provided by the first direct current power source can change the differential reference voltages, obtaining a reference for to-be-detected amplitude of the signals. Signal amplitude is detected with high precision, and detection reliability of a peak detecting circuit is improved.
US10855263B2
Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.
US10855258B1
This application relates to methods and apparatus for voltage control, and in particular to maintain safe voltages for components of audio driving circuits that are operable in a high voltage mode. An audio driving circuit (100) may include a power supply module (106) and may be operable such that, in use, a voltage magnitude at a source terminal of at least a first transistor (306, 309, 603, 605) of the audio driving circuit can exceed its gate-source voltage tolerance. A voltage generator (111P) is configured to output a first intermediate voltage (VSAFEP) to an intermediate voltage path for use as a gate control voltage for at least the first transistor, to maintain its gate-source voltage below tolerance. An intermediate path voltage clamp (114P) is provided for selectively clamping the intermediate voltage path to a voltage level, so as to maintain the magnitude of the gate-source voltage of the first transistor below tolerance. The voltage clamp (114P) is enabled by a reset condition (RST) for the audio driving circuit.
US10855254B2
Systems for calibrating impedances caused by a first component and a second component of a voltage-mode transmitter driver are described herein. The first component includes a first transistor and a first resistor connected to the first transistor, wherein the first component is connected to a voltage source and an output end of the voltage-mode transmitter driver, respectively. The second component includes a second transistor and a second resistor connected to the second transistor, wherein the second component is connected to the output end of the voltage-mode transmitter driver, and a third transistor, respectively. A first gate of the third transistor is applied with a first tunable gate voltage, and the first tunable gate voltage is configured to be tuned to calibrate a first impedance between the output end and a ground to match with a second impedance between the voltage source and the output end.
US10855243B2
A mobile communication system. The system has a housing comprising an interior region and an exterior region and a processing device provided within an interior region of the housing. The system has an rf transmit module coupled to the processing device, and configured on a transmit path. The system has a transmit filter provided within the rf transmit module. In an example, the transmit filter comprises a diplexer filter comprising a single crystal acoustic resonator device.
US10855240B2
Improved structures for spatial power-combining devices are disclosed. A spatial power-combining device includes a plurality of amplifier assemblies and each amplifier assembly includes a body structure that supports an input antenna structure, an amplifier, and an output antenna structure. According to embodiments disclosed herein, the body structure comprises a material that is configured to provide the spatial power-combining device with reduced weight while maintaining good thermal dissipation for heat generated by the amplifiers. In certain embodiments, the body structure may comprise an allotrope of carbon such as graphite or graphene, among others. In certain embodiments, the body structure may include one or more thermal vias configured to dissipate heat from the amplifier.
US10855230B2
Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.
US10855221B2
There is provided a cladding member (13) formed of a supporting body portion (67) having mounts (54) and a head portion (12), and an absorber surface portion (70) having a peripheral boundary wall (71) defining a recess into which a solar cell array (removed in this view for clarity) is bonded. The supporting (67) and absorber surface (70) body portions are pressure moulded from polyvinyl ester/glassfibre (30%)/fire retardant (40%)/pigment sheet moulding compound. Complementary bonding portions (72) form a glue line in assembly and have complementary water passages (73) defined therebetween. The bonding portions (72) contrive a generally sinusoidal glue space (74) that is longer that the transverse sectional dimension of the boding portions (72), cooperating with the adhesive system to resist water pressure in the passages (73).
US10855210B2
In an example, a method includes interacting electric fields from charges in conductors in different inertial reference frames to effect motion. The example method implements the mathematical framework that divides electric fields from charges in different inertial reference frames into separate electric field equations in electrically isolated conductors. The example method may implement the interaction of these electric fields to produce a force on an assembly that can, by way of illustration, propel a spacecraft using electricity without other propellant(s).
US10855203B2
A cascaded architecture composed of interconnected blocks that are each designed to process constant power and eliminate bulk energy storage are provided. Further, local controls within each block natively achieve both block- and system-level aims, making the system modular and scalable. Further methods of providing power conversion using such interconnected clocks are also provided.
US10855199B2
A method of discharging a Modular Multilevel Converter (MMC) includes a plurality of phase legs connected in delta configuration. Each leg includes a plurality of series connected submodules, each submodule including an energy storage. The method includes disconnecting the MMC from an electrical grid, discharging the energy storages by means of a circulating current, and reconnecting the MMC to the electrical grid. The discharging includes, for each phase leg, setting a voltage reference, and sequentially selecting submodules in zero state by means of a sorting algorithm for switching each of the selected submodules to plus or minus state until the voltage deviation from the set voltage reference of the energy storage of each submodule in the phase leg is within a predefined range.
US10855197B2
A power supply system includes a power supply assembly, an auxiliary power circuit and a control unit. The power supply assembly converts input power into a first DC power when the input power outputted from an input power source is normal. The auxiliary power circuit includes at least one energy storage unit for providing a second DC power and power converter electrically connected between the energy storage unit and the load for converting the second DC power into an individual auxiliary power. The control unit drives the auxiliary power circuit to provide an overall auxiliary power to the load when the input power is normal and a transient power required by the load is greater than a upper limit rated value of an output power outputted from the power supply assembly, so as to compensate a difference value between the transient power and the upper limit rated value.
US10855194B2
A high frequency power supply system provides highly regulated power and frequency to a workpiece load where the highly regulated power and frequency can be independent of the workpiece load characteristics by inverter switching control and an inverter output impedance adjusting and frequency control network that can include precision variable reactors with a geometrically-shaped moveable insert core section and a stationary split-bus section with a complementary geometrically-shaped split bus section and split electric terminal bus section where the insert core section can be moved relative to the stationary split-bus section to vary the inductance of the variable reactors.
US10855193B2
A power conversion unit includes an AC/DC converter converting alternating-current power supplied from an AC power supply into direct-current power to charge a high-voltage battery with the direct-current power and a step-down DC/DC converter generating an intermediate voltage provided by stepping down a voltage of direct-current power supplied from the high-voltage battery. A constant-voltage DC/DC converter outputs, to a low-voltage load unit, direct-current power provided by stepping down the intermediate voltage of direct-current power output from the step-down DC/DC converter at a constant step-down ratio.
US10855190B2
A magnetic integrated device is disclosed, the device includes: a first magnetic core base and a second magnetic core base that are parallel and a first magnetic core column, a second magnetic core column, and a third magnetic core column that are located between the first magnetic core base and the second magnetic core base; and a first winding, a second winding, and a third winding are wound on the first magnetic core column, the second magnetic core column, and the third magnetic core column respectively in a same manner to form a closed magnetic flux loop, where the first winding, the second winding, and the third winding are separately used for connecting to a branch of a three-phase parallel circuit, and in all branches of the three-phase parallel circuit, values of currents are the same, and a difference between each two current phases is 120 degrees.
US10855189B2
A control apparatus for a resonant converter that receives a direct current (DC) voltage of a bulk capacitor. The control apparatus includes a forced turn-off control circuit that receives a resonance current detection signal, which has been produced by shunting a resonance current flowing through the resonant converter and converting the shunted resonance current to a voltage, outputs a forced turn-off signal in response to the resonance current detection signal falling between a first variable threshold and a second variable threshold that is smaller than the first variable threshold, and varies the first variable threshold and the second variable threshold in accordance with an input voltage inputted to the forced turn-off control circuit by dividing the DC voltage of the bulk capacitor.
US10855186B2
Resonant power converters that replace the conventional impedance matching stage with series or parallel connections between resonant inverters and resonant rectifiers are provided. Two or more resonant rectifiers can be connected in series or in parallel to the resonant inverter to provide impedance matching. Similarly, two or more resonant inverters can be connected in series or in parallel to the resonant rectifier to provide impedance matching. Electrical isolation of DC voltage between input and output is provided using only capacitors.
US10855183B1
Methods and circuits are provided for controlling an electronic switch such that it may be controlled by an external control signal, such as a PWM signal, or be set to operate in an active-diode mode, wherein current is allowed to flow through the switch in only one direction. The described circuits are configured to autonomously control the electronic switch, such that no external control signal is required when the active-diode mode is used. The provided techniques allow electronic switches to be efficiently used as part of a power stage or part of an active rectifier, so as to support bi-directional switched-mode power supplies, motor/generator drivers, and related electric circuits that require bi-directional power flow. By reusing electronic switches thusly and implementing an active-diode mode, the circuitry is minimized while maintaining good power efficiency.
US10855182B2
A power conversion circuit includes an error amplifying circuit, a first comparison circuit, a second comparison circuit and a control circuit. The error amplifying circuit provides an output signal. The first comparison circuit, coupled to the error amplifying circuit, receives the output signal and a ramp signal to generate a first comparison signal. The second comparison circuit receives an output voltage and a first reference voltage and provides a second comparison signal. The control circuit, coupled to the error amplifying circuit, the first comparison circuit and the second comparison circuit, provides a control signal to control the error amplifying circuit according to the first comparison signal, the second comparison signal and an enabling signal. In a first operation mode of error amplifying circuit, the output signal is an error amplifying signal. In a second operation mode of error amplifying circuit, the output signal is a second reference voltage.
US10855175B2
A high voltage generator includes a voltage converting device configured to increase a level of an input voltage and output an output voltage having a level higher than the level of the input voltage. The high voltage generator also includes a precharge controller configured to gradually increase the level of the input voltage up to a level of an external voltage based on a reference voltage and the output voltage.
US10855170B2
A power management integrated circuit (PMIC) is provided for extracting power from an energy harvester. The PMIC includes a voltage converter to convert an input power at a voltage Vin into an output power at an output voltage Vout_VC. The voltage converter includes, in addition to a main voltage converter circuit, a cold-start circuit for starting the voltage converter from an OFF state. The PMIC further includes an input terminal for receiving a voltage VEN-CS proportional to the converter input voltage Vin and a voltage comparator for comparing the voltage VEN-CS with a reference voltage Vref. A controller enables the cold-start circuit when VEN-CS≥Vref.
US10855169B1
An on-board charger (OBC) for charging a traction battery of an electric vehicle includes a primary phase, a secondary phase, and a pre-charge circuit. Each phase includes a circuit having an input and an output. The primary phase circuit input is connectable to a mains supply to connect the primary phase to the mains supply. The secondary phase circuit input has an input capacitor. The pre-charge circuit is connected between the circuit outputs and is switchable between an opened state in which the pre-charge circuit disconnects the circuit outputs and a closed state in which the pre-charge circuit connects the circuit outputs. When the pre-charge circuit is in the closed state, an electrical current may flow through the pre-charge circuit from the primary phase circuit output to the secondary phase circuit output and through the secondary phase circuit to the input capacitor to charge the input capacitor.
US10855164B2
A switch-mode power supply and a zero current detector for use therein. A zero current detector includes an input stage and an output stage. The output stage is coupled to the input stage. The output stage includes a detector output terminal, a first transistor, and a second transistor. The first transistor includes an input terminal and a control terminal. The input terminal is coupled to the detector output terminal. The control terminal is coupled to the input stage. The second transistor includes an input terminal, a control terminal, and an output terminal. The input terminal is coupled to the control terminal of the first transistor. The control terminal is coupled to the input terminal of the second transistor. The output terminal is coupled to ground.
US10855162B2
The present invention provides a secondary side of a linear motor, which mainly includes a base, a combining mechanism and multiple magnetic members, wherein the base has multiple plates that are sequentially stacked into a block; the combining mechanism is configured to combine the plate-shaped bodies; and the magnetic members are disposed on the base in a separated manner.
US10855150B2
A device may be used to assemble a rotor segment of an electric machine. The rotor segment may include a rotor shaft, a laminated core joined to the rotor shaft, and two pressure elements that clamp the laminated core. A method for assembling the rotor segment may involve positioning the rotor shaft in the device and orienting the rotor shaft using an orienting means of the assembly device, positioning the laminated core and at least one of the first or second pressure elements within a clamping means of the device, orienting the laminated core by means of a positioning module of the clamping means, and moving the rotor shaft relative to the clamping means such that the laminated core is pushed onto the rotor shaft and the at least one of the first or second pressure elements is connected to the rotor shaft.
US10855144B2
An electrical winding topology having a core and a plurality of windings is provided. The plurality of windings is operatively coupled to the core, where at least one of the plurality of windings includes an evaporator section and a condenser section. Further, at least a portion of one or more of the plurality of windings includes heat pipes.
US10855136B2
A cooling unit of a drive motor includes: a fixing member installed on an inner wall surface of a motor housing and configured to fix a stator core of the drive motor, wherein the fixing member has a ring shape, includes a flow path formed therein in order to allow a cooling medium to flow, and includes a cooling medium inlet and a cooling medium outlet formed to be connected to the flow path, the flow path includes a first path connecting the cooling medium inlet and the cooling medium outlet to each other at one side and a second path connecting the cooling medium inlet and the cooling medium outlet to each other at another side, and the first and second paths have different flow cross sections and are connected to each other.
US10855132B2
A bus bar unit includes: a plurality of bus bars arranged to be laminated, the respective bus bars having conductivity, the respective bus bars having a hole part; an insulating member interposed between the bus bars, the insulating member having insulating property, the insulating member having a hole part; a positioning member formed by insulating resin, the positioning member having a pin protruding in direction of laminating the bus bars, the pin being inserted through the hole parts of the bus bars and the hole part of the insulating member; and a fixing part provided at a tip end of the pin, the fixing part being configured to fix the bus bars and the insulating member.
US10855131B2
An assembly for an electric machine including a core with a plurality of teeth extending radially inward from the core, the plurality of teeth defining a plurality of slots for receiving coils, a plurality of coils, each coil wrapping around a respective tooth, a separator in one of the slots including a first leg joined at an angle to a second leg for separating adjacent coils within the slot, an insert between the first leg and the second leg for at least partially filling a space between the first leg and the second leg, and a potting filling space within the slot between the separator, the plurality of coils, and the insert.
US10855124B2
An electric motor comprising: a stator assembly; a rotor assembly; and a support body. The stator assembly comprises a plurality of stator elements, and the rotor assembly comprises a shaft to which is mounted at least a first and a second bearing mounted either side of a permanent magnet. The support body comprises an elongate central part, and first and second bearing seats positioned axially at opposite ends of the elongated central part to each other, and the elongate central part defines a plurality of openings each configured to receive one of the plurality of stator elements.
US10855122B2
Provided is a stator for rotating electrical machine that can avoid the sagging of teeth stacked at the distal ends under the self-weight. A stator core is a laminate of metal foil members stacked in a direction of a rotation axis of the rotating electrical machine. Each tooth has a pair of side walls facing the neighboring teeth in the circumferential direction. The stator includes a pair of insulating reinforcing members so as to become a bridge between the corresponding tooth and a part of the yoke and sandwich the corresponding tooth from both sides in the direction of the rotation axis while exposing the pair of side walls; insulating fixing members, each fixing member fixing the corresponding pair of reinforcing members to the corresponding tooth while wrapping around the pair of reinforcing members and tooth; and coils formed as distributed windings at the teeth fixed with the fixing members.
US10855121B2
Provided is a rotary electric machine capable of reducing an amount of leakage magnetic flux passing through connecting portions. A cutout portion is formed in the connecting portion so as to be located on a side closer to a magnetic air gap portion. The connecting portion has a slot portion-side thin connecting portion formed so as to be closer to a slot portion than the cutout portion. A slot projecting portion projecting from the slot portion toward the magnetic air gap portion with respect to the slot portion-side thin connecting portion is formed in a portion of the connecting portion that is shifted in the circumferential direction from a portion of the connecting portion in which the slot portion-side thin connecting portion is formed. The slot projecting portion is arranged on each of circumferential sides of the cutout portion.
US10855108B2
A wireless device is provided and includes a coil assembly. The coil assembly includes a first coil, a second coil, a first contact, a second contact, and a third contact. The second coil is configured to be connected to the first coil in series. The first contact is configured to be connected to a first end of the first coil. The second contact is configured to be connected between the first coil and the second coil. The third contact is configured to be connected to a second end of the second coil. The first contact, the first coil and the second contact form a first circuit loop, and the first contact, the first coil, the second coil and the third contact form a second circuit loop.
US10855100B2
A power supply control apparatus is applied to a power supply system that includes an opening and closing unit that has a plurality of switches that are connected in series on an energization path over which energization from a voltage source is performed and a plurality of diodes that are respectively connected in parallel to the plurality of switches, in which the plurality of diodes include diodes that are arranged in opposite directions to each other. The power supply control apparatus includes a determining unit determining that an abnormal state has occurred in which a current is flowing to any of the plurality of diodes in a state in which the plurality of switches are turned off, and a control unit controlling the switch that is connected in parallel to the diode through which the current is flowing to an on-state, when the abnormal state is determined to have occurred.
US10855096B2
A quick charger for a vehicle performs normal charging or quick charging depending on whether a device connected thereto supports quick charging. The quick charger includes: an input terminal receiving power from a vehicle; an output port configured to be connected to an electronic device and comprising a power port and a communication port; and a charging voltage changing module configured to convert a voltage of the power applied to the input terminal into a normal charging voltage or a quick charging voltage larger than the normal charging voltage, depending on a level of a voltage sensed at the communication port connected to the electronic device, wherein the electronic device is charged with the normal charging voltage at a normal speed and is charged with the quick charging voltage at a faster speed than the normal speed. With the above-described configuration, the quick charger can automatically perform normal charging or quick charging depending on the type of the electronic device connected thereto.
US10855094B2
A method of displaying information on a display is provided. The method includes: receiving a request to display, on the display, information indicating whether each of a plurality of battery packs associated with the display, is mounted on a device of a plurality of devices associated with the display; in response to the request, displaying, on a monitor of the display, information indicating whether or not a battery pack of the plurality of battery packs associated with the display is mounted on each device of the plurality of devices associated with the display; receiving a selection of a battery pack from the plurality of battery packs displayed on the display; and in response to the selection of the battery pack, displaying information on the selected battery pack. Each of the plurality of battery packs is mountable on the plurality of devices.
US10855092B2
A device for holding and charging an electronic cigarette element is disclosed. The device includes a protective case element configured for coupling to a mobile computing device, the case element including a rechargeable battery, a first power port in the case element, the first power port conductively coupled to the rechargeable battery and configured for accepting external power for recharging the rechargeable battery, a cavity in the case element, wherein the cavity is configured to accept an electronic cigarette element, and a charging terminal located in the cavity such that when the electronic cigarette element is inserted into the cavity, one end of the electronic cigarette element contacts the charging terminal, and wherein the charging terminal is conductively coupled to the rechargeable battery, wherein when the electronic cigarette element contacts the charging terminal, the rechargeable battery recharges a battery of the electronic cigarette element.
US10855091B1
In one aspect, an electronic apparatus may include a base and an electrode. In one embodiment, the electrode can be cylindrical with a threaded portion on top of the electrode, and the threaded portion can be used to secure another electronic device with corresponding threads. For example, the electrode can be used to connect with a camera having an electrode and a corresponding threaded portion. More specifically, the camera can be secured on the electrode through the threaded portions and when the camera is fully secured on the electrode, the electrode can be in contact with the electrode to electrically connect with the camera.
US10855089B2
A charging control device includes a detector detecting a temperature of a battery; a controller causing the charger to stop charging the battery in response to the temperature of the battery falling outside a first range during the charging of the battery; an obtainer obtaining, from the charger, information that is capable of identifying a charging characteristic of the charger; a range setter setting the first range to be a temperature range that corresponds to the charging characteristic of the charger based on the information obtained in the obtainer.
US10855087B1
Exemplary power supply systems according to the present invention include circuitry that is configured to provide DC power and configured to receive a input signal that originates from a portable electronic device (the “PED”) and to provide a output signal to be sent to the PED. Such circuitry is configured to be coupled to the PED via a connector having a first, second, third, and fourth conductor. Such a connector is configured to be detachably mated with a power input interface of the PED to transfer the DC power to the PED, a ground reference to the PED, the input signal from the PED to the circuitry, and, in coordination with the input signal, the output signal from the circuitry to the PED, which is usable by the PED in connection with control of charging a battery of the PED based on the DC power provided by the circuitry.
US10855083B2
A generator system, including first and second generators each having an inverter circuit outputting AC, a connection circuit connecting the generators through a power line, a master-slave determining unit determining one of the generators as a master generator, and to determine other of the generators as a slave generator, a data acquiring unit acquiring an output data of the master generator, and a synchronization controlling unit controlling switching operation of the inverter circuit of the slave generator based on the output data of the master generator to synchronize an output data of the slave generator with the output data of the master generator, wherein the master-slave determining unit determines one of the generators that starts earlier as the master generator, and when the generators start simultaneously, to determine one of the generators as the master generator in accordance with a predefined rule.
US10855077B2
A utility management device, comprising an input for receiving a utility consumption signal for a premises, an output for outputting utility management information, and a processor configured to monitor the input utility consumption signal for a change in magnitude. If a change is detected, the processor is configured to identify an appliance event corresponding to the change, obtain information relating to the projected utility consumption of the appliance for an upcoming time period, update a projected utility consumption of the premises based on the obtained information, determine whether any projected stored and/or generated utility amount at the premises is sufficient for the projected utility consumption of the premises, and, if not sufficient, cause the device to output a request to receive a utility amount from one or more other premises connected to the premises via a communication network.
US10855073B2
A method of and apparatus for protecting a MEMS switch is provided. The method and apparatus improve the integrity of MEMS switches by reducing their vulnerability to current flow through them during switching of the MEMS switch between on and off or vice versa. The protection circuit provides for a parallel path, known as a shunt, around the MEMS component. However, components within the shunt circuit can themselves be removed from the shunt when they are not required. This improves the electrical performance of the shunt when the switch is supposed to be in an off state.
US10855071B2
A motor drive includes a rectifier bridge for connection with mains, a converter bridge configured to connect with an elevator motor and an intermediate DC circuit in-between. A capacitor and/or battery is connected between positive and negative branches of the intermediate DC circuit. At the mains side of the rectifier bridge a controlled main relay with contacts are configured to connect or disconnect the rectifier bridge with the corresponding mains phase. The motor drive comprises a charging circuit which comprises a charging switch connected with a current limiting component. The motor drive comprises a voltage sensor between positive and negative branches of the intermediate DC circuit. The voltage sensor is connected to a circuit comprising a reference value and a comparator. The evaluation circuit is configured to compare the actual sensor signal of the voltage sensor to the reference value and to operate the main relay based on the comparison.
US10855066B2
Disclosed herein is an adjustable mounting assembly for mounting an electrical module relative to a supporting surface. The assembly comprises: mounting means adapted for embedded anchorage relative to the supporting surface; a holder having an aperture for receiving and holding the electrical module, the holder being adapted for moveable engagement with the mounting means to facilitate adjustment of a position of the electrical module relative to the supporting surface; and fastening means for fastening the holder to the mounting means, the fastening means being accessible for unfastening and refastening via the aperture to facilitate re-adjustment of the position of the electrical module relative to the supporting surface.
US10855063B2
A method in the manufacturing of an insulated electric high voltage DC termination or joint includes providing an insulated electric high voltage DC cable including a high voltage DC conductor, a polymer based insulation system surrounding the high voltage DC conductor, the polymer based insulation system including an insulation layer and a semiconducting layer surrounding the insulation layer, and a grounding layer surrounding the semiconducting layer; removing the grounding layer and the semiconducting layer in at least one end portion of the high voltage DC cable, mounting a field grading adapter or joint body in the at least one end portion of the high voltage DC cable; and subjecting the insulation layer of the polymer based insulation system in the at least one end portion of the high voltage DC cable for a heat treatment procedure, while being covered by the mounted field grading adapter or joint body.
US10855062B2
A cabinet comprising an outer wall which encapsulates an internal space comprising electronic components, the outer wall having a rupture line forming a release wall portion which by rupturing of the rupture line in response to an increased pressure in the internal space can be released and thereby define an opening forming arc-vent for the internal space. To protect against penetration of objects of a predetermined size into the electronic components, the cabinet further comprises a ventilation-open inner lining arranged in the internal space to cover the opening. If arcing should occur, the increased pressure may rupture the line and the opening will allow venting. In this situation, the inner lining prevents against penetration.
US10855059B2
A compartment-partitioning and busbar-supporting device for a cabinet for a low voltage electrical switchboard an insulating body having a substantially rectangular shape with a first surface configured for coupling with one or more busbars and a second surface configured for coupling with one or more electrical apparatuses, said first and second surfaces being delimited by a first and a second opposite side substantially parallel to each other and configured for coupling with a vertical uprights or horizontal crossbars of the supporting structure of the low voltage electrical switchboard, and a third and a fourth opposite sides substantially parallel to each other and perpendicular to said first and second opposite sides and configured for allowing vertical stacking of a plurality of said compartment-partitioning and busbar-supporting devices in correspondence of said third and fourth opposite sides, said first surface being provided with a plurality of retaining pairs of first and second retaining means facing each other and defining a retaining space for a busbar among them, the retaining pairs for a given busbar being aligned in a direction parallel to said first and second opposite sides and the retaining pairs for different busbars being spaced apart in a direction parallel to said third and a fourth opposite sides, said second surface being provided with a plurality of openings configured for allowing insertion of connection means between said electrical apparatuses and said busbars through said compartment-partitioning and busbar-supporting device.
US10855057B2
In a spark plug for an internal combustion engine, a cylindrical insulator is arranged radially inside a cylindrical ground electrode, and includes an insulator protruding portion protruding further toward a distal end side in an axial direction than a distal end of the ground electrode. A center electrode is held radially inside the insulator, and includes an exposed portion exposed from a distal end of the insulator protruding portion. The spark plug generates a discharge from the exposed portion to the ground electrode, in a discharge gap formed along a surface of the insulator protruding portion. At least one of the exposed portion and the insulator protruding portion includes a flow inlet that is open on an outer circumferential surface thereof, a flow outlet that is open toward the discharge gap, and a communication passage communicating between the flow inlet and the flow outlet.
US10855051B2
What is shown is a method for manufacturing a semiconductor light source. The semiconductor light source has a substrate and a layer sequence arranged above the substrate, the same having a light-emitting layer and an upper boundary layer arranged above the light-emitting layer. The layer sequence is patterned in order to form a light-emitting stripe for defining the semiconductor light source and an alignment stripe, extending in parallel thereto, as a horizontal alignment mark at the same time. Then, a cover layer is applied on the patterned layer sequence and a part of the cover layer is removed in order to expose the alignment stripe and expose a region of the layer sequence outside the light-emitting stripe and spaced apart from a light-entrance edge or a light-exit edge of the light-emitting stripe as a vertical alignment mark.
US10855049B2
A pulse laser apparatus (100) for creating laser pulses (1), in particular soliton laser pulses (1), based on Kerr lens mode locking of a circulating light field in an oscillator cavity (10), comprises at least two resonator mirrors (11, 12, . . . ) spanning a resonator beam path (2) of the oscillator cavity (10), at least one Kerr-medium (21, 22, 23) for introducing self-phase modulation and self-focusing to the circulating light field in the oscillator cavity (10), at least one gain-medium (31) for amplifying the circulating light field in the oscillator cavity (10), and a tuning device (40) for setting a first mode-locking condition and a second mode-locking condition of the oscillator cavity (10) such that an intra-cavity threshold-power for mode-locking at the first mode-locking condition is lower than that at the second mode-locking condition, wherein the first mode-locking condition is adapted for starting or shutting-down of the Kerr lens mode locking and the second mode-locking condition is adapted for continuous Kerr lens mode locking and a resonator-internal peak-power of the circulating light field is higher at the second mode-locking condition than at the first mode-locking condition. Furthermore, a method of operating a pulse laser apparatus is described.
US10855031B2
Apparatuses for securing a memory card. One example apparatus can include a slot coupled to a printed circuit board (PCB), wherein the slot is configured to receive a memory card to provide electrical connection between the PCB and the memory card and a cover coupled to the PCB and configured to enclose the memory card when in a closed position and maintain electrical connection between the memory card and the PCB when in the closed position.
US10855028B1
A plug connector includes a plug housing having a mating end at a front of the plug housing for mating with a mating connector. The plug housing has an upper wall, an end wall extending from the upper wall, and side walls extending from the upper wall. The plug housing has a mating chamber defined by the upper wall, the end wall and the side walls. The mating chamber is open at the front. The end wall is opposite the front at a rear of the mating chamber. The plug connector includes a circuit card held by the plug housing. The circuit card extends into the mating chamber for mating with the mating connector. The circuit card has plug contacts. The plug connector includes a mating spring coupled to the end wall. The mating spring has a spring arm extending into the mating chamber. The spring arm has a mating interface configured to engage a mating end of the mating connector to bias the end wall away from the mating end of the mating connector.
US10855027B2
A card-type storage device and a slot device, which are capable of preventing lowering of the reliability due to repeated insertion and removal of the storage device. A card medium includes card thermal contacts each having a contact surface which intersects with a thickness direction of the card medium. A first card upper guide surface restricts the position of the card medium in the thickness direction to a first position. An escape portion restricts the position of the card medium in the thickness direction to a different position from the first position. A second card upper guide surface links the first card upper guide surface and the escape portion.
US10855026B2
An electrical connector includes a plug that mates with a receptacle. In a medical application, the plug is connected to electrical leads that pass through a patient's skin to an implanted medical device in the patient's body, while the receptacle is connected to external medical equipment. The plug is small in diameter so the size of the opening in the patient's skin can be minimized. All electrical contacts in the plug are on internal portions. The receptacle includes annular contacts that contact the internal electrical contacts on the plug when the plug and receptacle are properly mated. When the plug is plugged into the receptacle, spring-loaded retention arms in the receptacle lock into place on the plug, retaining the plug in the receptacle.
US10855024B2
An electrical connector having electrical terminals and a housing. The housing has a terminal-receiving portion with terminal-receiving cavities for receiving the electrical terminals therein. At least one latch-receiving slot is positioned between adjacent terminal-receiving cavities. A cover portion is provided for covering the terminal-receiving cavities and the terminals. The cover portion has latches which cooperate with the at least one latch-receiving slot when the cover portion is moved to a closed position. A hinge portion connects the terminal-receiving portion to the cover portion. The hinge is deformable to allow the cover portion to move between an open position in which the terminals can be inserted and removed from the terminal-receiving cavities of the terminal-receiving portion and the closed position in which the terminals are secured in the terminal-receiving cavities of the terminal-receiving portion.
US10855020B1
A card edge connector includes a housing including a card slot open to a cavity and a contact assembly received in the cavity. The contact assembly has a contact positioner holding upper contacts in an upper contact array and lower contacts in a lower contact array. The contact positioner has a positioner card slot. The contacts include intermediate portions extending between mating beams and contact tails. The contact arrays include separate and discrete front and rear contact holders. The front contact holder is positioned between the mating beams and the intermediate portions. The rear contact holder is positioned between the intermediate portions and the contact tails.
US10855014B1
A connector (10) used with a high-current terminal (100) includes a main body (1) and a conductive spacer (2). The main body (1) has a connecting portion (11) disposed at one end thereof and a pluggable portion (12) disposed at the other end thereof. The high-current terminal (100) is plugged into the pluggable portion (12). The conductive spacer (2) is disposed between the pluggable portion (12) and the high-current terminal (100). The conductive spacer (2) has a plurality of outer projections (21) pressed against the pluggable portion (12) and a plurality of inner projections (22) pressed against the high-current terminal (100). Thus, the number of electrical contact points is increased by means of the outer projections (21) and the inner projections (22) disposed between the pluggable portion (12) and the high-current terminal (100) such that the connector (10) has excellent electric conductivity and current adjustment capability.
US10855009B2
Provided is a press-fit pin. The press-fit pin according to an embodiment of the present invention includes: a press unit press-fitted into a through hole formed on a board, which is press-fitted into an inner surface of the board including the through hole, pressurized toward a long hole formed inside the press unit, applies a repulsive force to the inner surface of the board through an elastic force, and maintains a contact with the inner surface of the board; a first terminal which is extended for a predetermined length from one side of the press unit along a longitudinal direction of the press unit and is disposed at the upper side of the board when press fitting the press unit; and a second terminal which is extended for a predetermined length from the other side of the press unit along the longitudinal direction of the press unit and is disposed at the lower side of the board, when press fitting the press unit, wherein the press unit includes a plurality of press-fit parts which faces each other along a width direction of the press unit based on the long hole, is pressurized to the inside along the width direction of the press unit and a thickness direction of the press unit, which crosses the width direction of the press unit, when the plurality of press-fit parts is press-fitted into the through hole, and applies a repulsive force toward the width direction of the press unit and the thickness direction of the press unit using an elastic force.
US10855007B2
A plug-in connection includes a first and second coupling part. The first coupling part includes a first contact element, an electrical cable, an insulation sleeve, and a first housing. The first contact element includes a base region and an outer region with an edge region, an external shell surface, and a slot. The electrical cable includes an electrical conductor, a connection region, and an insulation for the electrical conductor. The insulation sleeve surrounds the outer region and includes an external and internal shell surface. The first housing surrounds the base region, the insulation sleeve's external shell surface, and the connection region. The second coupling part includes a second contact element with an external shell surface over which the first contact element's outer region is slidable, and a second housing which encloses the second contact element and together therewith forms an annular space into which the first housing is insertable.
US10855004B2
A coaxial cable connector comprising a sleeve, nut, post, and annular flange is provided. When the post is assembled to the nut, the annular flange to the post, and post, annular flange and nut to the sleeve, a proximal post engagement portion of the post is near to a protrusion ridge of the nut, and a proximal flange engagement end of the annular flange is flush with an annular inward protrusion of the nut and post ridge and post outer surface of the post. An annular space is formed between the proximal flange engagement end and a distal flange end of the annular flange and post outer surface and a distal post tapered end of the post. A plurality of deformed indentations is formed on an inner surface of the sleeve via a plurality of engagement protrusions of the nut, each having a tapered side and a distal side.
US10854996B2
The disclosed structures and methods are directed to transmission and reception of a radio-frequency (RF) wave. An antenna comprises a stack-up structure having a first control layer, a second control layer, a first and a second parallel-plate waveguides, and a plurality of through vias. The antenna further comprises a first central port and a second central port being configured to radiate RF wave into the two parallel-plate waveguides independently; vertical-polarization peripheral radiating elements integrated with the first control layer and configured to radiate RF wave in vertical polarization; and horizontal-polarization peripheral radiating elements integrated with the second control layer and configured to radiate RF wave in horizontal polarization. Each vertical-polarization peripheral radiating element is collocated with one of the horizontal-polarization peripheral radiating element such that they cross each other. A central port for transmission of RF wave into the stack-up structure of the antenna is also provided.
US10854993B2
An antenna element including a base plate, a first ground clustered pillar projecting from the base plate, a second ground clustered pillar projecting from the base plate and spaced apart from a first side of the first ground clustered pillar is provided. The ground clustered pillars, the signal ears, and the ground ears can be shapes so that the capacitive coupling between the ears and the pillars is sufficient to allow them to be spaced further apart, thereby reducing the number of elements required in the phased array. In some embodiments, the ground ear can be directly machined with the base plate thereby obviating the need for the ground ear to be overmolded into the base plate with the signal ear. In other embodiments the phased array antenna can utilize elastomeric connectors to further improve the mechanical and electrical reliability of the connections of the phase array antenna.
US10854992B2
A radar transmitter transmits a radar signal through a transmitting array antenna at a predetermined transmission period, and a radar receiver receives a reflected wave signal which is the radar signal reflected by a target through a receiving array antenna. A transmitting array antenna and a receiving array antenna each include multiple subarray elements, the subarray elements in the transmitting array antenna and the receiving array antenna are linearly arranged in a first direction, each subarray element includes multiple antenna elements, the subarray element has a dimension larger than a predetermined antenna element spacing in the first direction, and an absolute value of a difference between a subarray element spacing of the transmitting array antenna and a subarray element spacing of the receiving array antenna is equal to the predetermined antenna element spacing.
US10854991B2
The present disclosure relates to a waveguide fed open slot antenna. In some examples, the antenna comprises a waveguide section, a slot, a matching load, a waveguide bottom extension, and a vertical metal wall. The waveguide section can be in the form of a rectangular waveguide or a substrate integrated waveguide (SIW). The slot can comprise a rectangle, with one of its long sides abutting the top surface of the waveguide section, and another long side abutting the matching load, while the two short sides do not connect any metal. The waveguide bottom extension can be rectangular. The end of the waveguide bottom extension and the edge of the matching load on the side close to the open slot can be connected together by the vertical metal wall. In this way, the slot can be excited.
US10854989B2
Embodiments discussed herein refer to systems and structures for focusing dispersal of electromagnetic signals. Focusing of the electromagnetic signals is achieved by a reflective lens that is constructed from several extremely high frequency focusing layers. Each focusing layer can include an extremely high frequency focusing window that, collectively, define the geometry of a cavity backed reflective lens and its ability to focus electromagnetic signal dispersion.
US10854982B2
A dielectric resonator antenna (DRA) includes: an electrically conductive ground structure; at least one volume of a dielectric material disposed on the ground structure; a signal feed disposed and structured to be electromagnetically coupled to the at least one volume of a dielectric material; and an electrically conductive fence disposed circumferentially around the at least one volume of a dielectric material, and electrically connected with and forming part of the electrically conductive ground structure.
US10854977B2
A three-broadside-mode patch antenna includes: a rotationally symmetric radiator; a patch, wherein the patch is separated from the rotationally symmetric radiator by a dielectric and configured to capacitively feed the rotationally symmetric radiator; and three antenna probes, connected to the patch, configured to provide three antenna ports corresponding to three respective broadside radiation polarizations.
US10854976B2
An antenna includes an electrical excitation component and a core component. The electrical excitation component has and input and a conducting component. The conducting component can conduct current from the input. The core component has a magnetic film, having a substrate and a magnetic material layer, wound around a rectangular mounting plate. The core component can have a magnetic current loop induced therein. The electrical excitation component is arranged such that concentric magnetic fields associated with current conducted through the electrical excitation component are additionally associated with a magnetic current loop within the core component.
US10854973B2
An antenna apparatus and an electronic apparatus are provided. The electronic apparatus includes the antenna apparatus. The antenna apparatus includes a radiator, a first and a second impedance control circuit. The radiator receives and transmits a radio frequency (RF) signal. The first impedance control circuit is electrically connected to the radiator and transmits the RF signal. The second impedance control circuit includes an impedance matching circuit and an inductor. The first end of the impedance matching circuit is electrically connected to the radiator. The impedance matching circuit adjusts the impedance matching of the radiator and transmits a sensing signal. The inductor is electrically connected to the second end of the impedance matching circuit. The inductor transmits a sensing signal, and blocks the RF signal. Accordingly, the structures of the antenna and the circuit can be simplified, and the influence between the RF signal and the sensing signal can be reduced.
US10854972B2
A multiple-frequency antenna device includes an antenna unit and a frequency switch unit. The antenna unit includes an insulating substrate on which grounded first and second conductive layers are disposed. The first conductive layer is further connected to a radio-frequency (RF) circuit. The frequency switch unit is connected to the antenna unit in parallel, and includes a switching component, and a frequency adjustment: component connected to the antenna unit. The multiple-frequency antenna device is resonant at a first resonant frequency when the switching component is switched to a first state, and is resonant at a different, second resonant frequency when the switching component is switched to a second state.
US10854971B1
Arrays that are deployable and can change their electromagnetic behavior by changing their shape are provided. An array can include a central panel and at least one foldable panel attached thereto. The central panel can include radiating elements on its upper surface while each foldable panel can have radiating elements on its bottom surface. The array is reconfigurable by each foldable panel being foldable onto the central panel such that its bottom surface then faces upward and covers part or all of the upper surface of the central panel.
US10854965B1
A ground shield is connected to a princted circuit board or antenna card in an antenna unit cell to cover a balun to prevent or inhibit the ability of a differential signal flowing towards or through the balun from coupling with a similar differential signal flowing through an adjacent antenna card in the antenna unit cell. This ground shield may be one of a pair of ground shields on the antenna card. Two ground shield can be positioned on opposing sides of the balun to enhance isolation thereof by shielding the differential signals flowing towards and through the balun from coupling with adjacent differential signals to thereby increase bandwidth performance of the antenna unit cell. The ground shields may be generally or substantially or totally planar so as to be conformal with a substrate or dielectric layer of the antenna card or printed circuit board.
US10854962B2
Disclosed is a cross loop antenna system for an aerial vehicle. In one embodiment, the cross loop antenna system includes a cross bar antenna and a ground plane. The cross bar antenna includes two thin coplanar perpendicular bars that intersect in the middle and are parallel to the ground plane. Each bar couples to the ground plane at each end, comprising an antenna loop. Thus, the cross loop antenna system comprises two intersecting single-fed loops. The antenna can operate at a wavelength that is approximately twice the length of the bars. In such an embodiment, the antenna system may be resonant. The distance between the bars and the ground plane may be relatively small, thus minimalizing the vertical profile of the antenna. The antenna may be operated as a dual-band antenna and may produce an omnidirectional radiation pattern. An aerial vehicle may include two such antennas.
US10854955B2
The present disclosure provides an electronic device, a mobile terminal and an antenna assembly. The electronic device includes: a case defining an accommodating groove; a movable support slidably connected to the case, and capable of moving out of or retracting into the accommodating groove; and a first antenna installed on the movable support. Since the first antenna may be ejected out of the accommodating groove along with the movable support, influence of other components disposed inside the electronic device on the first antenna may be reduced. Thus, the implementation of the present disclosure may improve antenna performance of the electronic device.
US10854951B2
The present disclosure provides an antenna package structure and an antenna packaging method for a semiconductor chip. The package structure includes an antenna circuit chip, a first rewiring layer, an antenna structure, a second metal connecting column, a second packaging layer, a second antenna metal layer, and a second metal bump. The antenna circuit chip, the antenna structure, and the second antenna metal layer are interconnected by using two rewiring layers and two layers of metal connecting columns.
US10854947B2
An electronic device is provided. The electronic device includes a housing, a display exposed through at least a portion of the housing, a battery disposed in the housing, an antenna module disposed in the housing and spaced apart from the battery, a first electronic component positioned between the antenna module and the battery, a first heat dissipation member disposed to partially overlap the first electronic component and to extend toward the antenna module, a frame disposed to partially overlap the first heat dissipation member, surround at least a part of the first electronic component, and form a part of an outer appearance of the electronic device, and a heat insulation member interposed between the frame and the first heat dissipation member.
US10854938B2
A phase shifter is disclosed and includes a first substrate comprising a phase change line; and a second substrate comprising an input line connected to an input port, a first output line connected to a first output port, a second output line connected to a second output port, and a connection line connecting the first output line and the second output line. The first substrate is disposed to face the second substrate and to be overlaid at a predetermined distance from the second substrate. A phase of a signal passing through a first portion of the phase change line changes by a first value according to a movement of the first substrate. The signal is branched into a first signal to be transmitted to the first output port and a second signal to be transmitted to the second output port.
US10854933B2
Presented are battery pack voltage-switching (“V-switch”) systems, methods for making/operating such systems, and multi-pack, electric-drive motor vehicles with battery pack V-switch capabilities. A method for controlling operation of a vehicle includes a vehicle controller receiving a voltage switch signal to change a voltage output of the vehicle's battery system. The vehicle controller determines if a speed of a traction motor is less than a calibrated base speed; if so, the controller transmits a pack isolation signal to a power inverter to electrically disconnect the traction battery packs from the traction motor. The vehicle controller determines if a bus current of a DC bus is less than a calibrated bus current threshold; if so, the controller transmits an open signal to open one or more pack contactor switches and a close signal to close one or more pack contactor switches thereby causing the vehicle battery system to output the second voltage.
US10854920B2
Provided are a solid electrolyte composition containing at least one dendritic polymer selected from the group consisting of dendrons, dendrimers, and hyperbranched polymers and a specific inorganic solid electrolyte, in which the dendritic polymer has at least one specific functional group, an electrode sheet for an all-solid state secondary battery and an all-solid state secondary battery for which the solid electrolyte composition is used, a method for manufacturing an electrode sheet for an all-solid state secondary battery, and a method for manufacturing an all-solid state secondary battery.
US10854919B2
A solid polymer electrolyte for a battery is disclosed. The solid polymer electrolyte includes solid polymer electrolyte including a diblock copolymer AB or a triblock copolymer of the BAB type, in which block A is an unsubstituted polyethylene oxide chain having a number-average molecular weight less than 80,000 g/mol; block B is an anionic polymer prepared from one or more monomers selected from vinyl monomers and derivatives thereof to which is grafted an anion of lithium salt, and a second monomer having cross-linking functions.
US10854916B2
Solid-state lithium ion electrolytes of lithium metal sulfide based composites are provided which contain an anionic framework capable of conducting lithium ions. An activation energy of the lithium metal sulfide composites is from 0.2 to 0.45 eV and conductivities are from 10−4 to 3.0 mS/cm at 300K. Composites of specific formulae are provided and methods to alter the composite materials with inclusion of aliovalent ions shown. Lithium batteries containing the composite lithium ion electrolytes are also provided. Electrodes containing the lithium metal sulfide based composites and batteries with such electrodes are also provided.
US10854897B2
Temperature control system and method for a fuel cell system are disclosed. The temperature control system includes a state detector, a control selector, a normal controller and an internal model controller. The state detector determines whether the fuel cell system is in a leakage condition based on a dynamic transfer function from an air flowrate provided to the fuel cell system to a fuel cell temperature. The control selector selects to switch between the normal controller and the internal model controller based on a determined result. The normal controller is configured for controlling an air flowrate of the fuel cell system which is not in the leakage condition. The internal model controller is configured for controlling the air flowrate of the fuel cell system in the leakage condition to control the fuel cell temperature. A fuel cell system with the temperature control system is also disclosed.
US10854883B2
A wire mesh including a warp which includes a first nickel alloy wire having a first peak tensile strength; and a weft which includes a wire including nickel having a second peak tensile strength, wherein the first peak tensile strength is greater than or equal to the second peak tensile strength, is provided. A current collector and a zinc-air battery that includes the wire mesh are also provided.
US10854880B2
An all-solid-state battery including a laminated body with a cathode current collecting layer, cathode active material layer, solid electrolyte layer, anode active material layer, and anode current collecting layer in this order, and a restraining member that applies a restraining pressure to the laminated body in a laminated direction; containing a conductive material, an insulating inorganic substance, and a polymer, is in at least one of a position between the cathode active material layer and the cathode current collecting layer, and a position between the anode active material layer and the anode current collecting layer; the content of the insulating inorganic substance in the PTC layer is 10 volume % or more and 40 volume % or less; and a proportion of a particle size D90 of the insulating inorganic substance, D90, to a thickness of the PTC layer, TPTC, regarded as D90/TPTC is 0.6 or more and 1.0 or less.
US10854877B2
An all-solid-state secondary battery including: a positive electrode layer; a negative electrode layer; and a solid electrolyte layer between the positive electrode layer and the negative electrode layer, wherein the positive electrode layer includes a sulfur-containing positive electrode active material, a halogen-containing sulfide solid electrolyte, and a conductive carbon material, and wherein the sulfur-containing positive electrode active material includes elemental sulfur and a transition metal disulfide.
US10854845B2
A display device may include a substrate having a first pixel area, a first electrode on the substrate; a passivation layer between the substrate and the first electrode, a second electrode on the first electrode, and an organic emission layer between the first electrode and the second electrode. The first pixel area may include an emission area and a non-emission area surrounded by the emission area.
US10854836B2
A light emitting device includes: a first electrode and a second electrode facing each other, an emissive layer disposed between the first electrode and the second electrode and including a quantum dot, an electron auxiliary layer disposed between the emissive layer and the second electrode and including a plurality of nanoparticles, and a polymer layer between a portion of the second electrode and the electron auxiliary layer, wherein the nanoparticles include a metal oxide including zinc, wherein the second electrode has a first surface facing a surface of the electron auxiliary layer and a second surface opposite to the first surface, and the polymer layer is disposed on a portion of the second surface and a portion of the surface of the electron auxiliary layer, and wherein the polymer layer includes a polymerization product of a thiol compound and an unsaturated compound having at least two carbon-carbon unsaturated bonds.
US10854833B2
The invention relates to a photovoltaic device (1), comprising a photovoltaic acceptor material (7) and a photovoltaic donor material (10), in which the photovoltaic device (1) comprises at least two carrier layers (2, 3), of which one carrier layer (2) has n-doped electron donors (6) and the other carrier layer has acceptor material (7) as p-doped or undoped electron acceptors, wherein the carrier layers (2, 3) are arranged with respect to one another such that they touch one another at least in sections, and the carrier layers (2, 3) are wetted or coated in filmlike fashion with a photovoltaic donor material (10). The carrier layers (2, 3), which are formed in particular from fibres (6, 7) composed of silicon carbide SiC, enable textile solar cells. Methods for producing the fibres (6, 7) and for producing the photovoltaic device (1) and textile structures formed therefrom are furthermore described. A photovoltaic device (1) is furthermore proposed, in which carrier elements of an individual carrier layer have a corresponding photovoltaically active construction by virtue of correspondingly applied layers.
US10854825B2
An organic semiconductor element functions as a strain sensor, and includes a substrate and an organic semiconductor layer formed on the substrate as a single-crystal thin film of an organic semiconductor that is a polycyclic aromatic compound with four or more rings or a polycyclic compound with four or more rings including one or a plurality of unsaturated five-membered heterocyclic compounds and a plurality of benzene rings. Since the organic semiconductor layer is formed as the single-crystal thin film, an identical crystal structure is obtained regardless of formation technique. Therefore, when the same strain is given, the same carrier mobility is obtained and uniform property is obtained with respect to the strain. Accordingly, it is possible to provide strain sensors having uniform property.
US10854823B2
Provided are a heterocyclic compound and an organic light-emitting device including the same. The heterocyclic compound is represented by Formula 1:
US10854820B2
The present disclosure provides a blue organic electroluminescent device comprising: a substrate; an anode layer disposed on the substrate; a light emitting layer disposed on the anode layer, the light emitting layer being formed from a blue organic fluorescent material and a hole-type organic host material, wherein the blue organic fluorescent material is 8.0% to 25.0% by mass of the hole-type organic host material; and a cathode layer disposed on the light emitting layer.
US10854819B2
A method of making a solid state semiconducting film. The method includes blending a non-conjugated semiconducting polymer matrix containing crystalline aggregates with intentionally placed conjugation-break spacers along the polymer backbone, and fully conjugated semiconducting polymer. The resulting blend is subjected to a film making method to result is a semiconducting film. A solid state semiconducting film comprising a non-conjugated semiconducting polymer matrix containing crystalline aggregates with intentionally placed conjugation-break spacers along the polymer backbone, and a fully conjugated semiconducting polymer, wherein the fully conjugated semiconducting polymer serves as tie chains to bridge crystalline aggregates from the non-conjugated polymer matrix. Devices made from these semiconductor films.
US10854813B2
Methods and devices based on the use of dopant-modulated etching are described. During fabrication, a memory storage element of a memory cell may be non-uniformly doped with a dopant that affects a subsequent etching rate of the memory storage element. After etching, the memory storage element may have an asymmetric geometry or taper profile corresponding to the non-uniform doping concentration. A multi-deck memory device may also be formed using dopant-modulated etching. Memory storage elements on different memory decks may have different taper profiles and different doping gradients.
US10854811B2
Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) switch. In particular embodiments, formation of a CEM switch may include removing of an exposed portion of a CEM film to form an exposed sidewall region bordering a remaining unexposed portion of the CEM film under or beneath a conductive overlay. The method may further include at least partially restoring properties of the exposed sidewall region to a CEM via exposure of the exposed sidewall region to one or more gaseous annealing agents.
US10854810B2
A passive magnetic device (PMD) has a base electrode, a multi-port signal structure (MPSS), and a substrate therebetween. The MPSS has a central plate residing in a second plane and at least two port tabs spaced apart from one another and extending from the central plate. The substrate has a central portion that defines a mesh structure between the base electrode and the central plate of the multi-port signal structure. A plurality of magnetic pillars are provided within the mesh structure, wherein each of the plurality of the magnetic pillars are spaced apart from one another and surrounded by a corresponding portion of the mesh structure. The PMD may provide a magnetically self-biased device that may be used as a radio frequency (RF) circulator, an RF isolator, and the like.
US10854800B2
A light emitting device includes a substrate, a first group of light emitting diode (LED) structures, a second group of LED structures, and a connection port is provided. The substrate has a first surface and a second surface opposite to the first surface. The first group of LED structures is disposed on one side of the first surface. The second group of LED structures is disposed on another side of the first surface opposite to the first group of LED structures. The connection portion includes at least an opening, and a first connection pad and a second connection pad electrically coupled to at least a part of the LED structures. The connection port is adapted to be coupled to other device through the opening. A light emitting module and an illuminating apparatus are also provided.
US10854789B2
A light-emitting device includes a first lead having a first lateral surface, a second lead having a second lateral surface, and a resin portion. The first lateral surface of a first lead facing a second lead has a first recess that is recessed so as to be away from the second lead toward the first lead in a top view, and is continuous with an end of a first groove. The second lateral surface of the second lead facing the first lead has a second recess that is recessed so as to be away from the first lead toward the second lead in the top view, and is continuous with an end of a second groove. In the top view, a part of the resin portion is continuously disposed between the end of the first groove and the end of the second groove.
US10854784B2
A method for producing an electrical contact on a semiconductor layer and a semiconductor component having an electrical contact are disclosed. In an embodiment a method includes providing a semiconductor layer, forming a plurality of contact rods on the semiconductor layer, wherein the contact rods are formed by a first material and a second material, wherein the first material is applied to the semiconductor layer and the second material is applied to the first material, and wherein a lateral structure of the first material is self-organized, forming a filling layer on the contact rods and in intermediate spaces between the contact rods and exposing the contact rods.
US10854776B1
A method for manufacturing a display panel comprising light emitting device including micro LEDs includes providing multiple donor wafers having a surface region and forming an epitaxial material overlying the surface region. The epitaxial material includes an n-type region, an active region comprising at least one light emitting layer overlying the n-type region, and a p-type region overlying the active layer region. The multiple donor wafers are configured to emit different color emissions. The epitaxial material on the multiple donor wafers is patterned to form a plurality of dice, characterized by a first pitch between a pair of dice less than a design width. At least some of the dice are selectively transferred from the multiple donor wafers to a common carrier wafer such that the carrier wafer is configured with different color emitting LEDs. The different color LEDs could comprise red-green-blue LEDs to form a RGB display panel.
US10854775B2
A method and a device for carrying out the method for transferring electronic components from a carrier substrate to a receiving substrate. The method comprises a positioning step in which a carrier substrate on which a plurality of electronic components arranged in a grid each adhere to a corresponding adhesion site by means of an adhesion which can be detached by laser radiation is positioned, in particular oriented, relative to a receiving substrate; a transferring step in which, while the positioning of the carrier substrate relative to the receiving substrate is maintained, the adhesion sites of the components of a transfer unit consisting of at least two of the components arranged on the carrier substrate are selectively irradiated with laser radiation such that the adhesion of the components of the transfer unit is selectively detached thereby from the carrier substrate at these adhesion sites, and the components of the transfer unit are each transferred to a grid position on the receiving substrate corresponding to the initial arrangement thereof in the grid on the carrier substrate.
US10854772B2
A system for transporting substrates and precisely align the substrates horizontally and vertically. The system decouples the functions of transporting the substrates, vertically aligning the substrates, and horizontally aligning the substrates. The transport system includes a carriage upon which plurality of chuck assemblies are loosely positioned, each of the chuck assemblies includes a base having vertical alignment wheels to place the substrate in precise vertical alignment. A pedestal is configured to freely slide on the base. The pedestal includes a set of horizontal alignment wheels that precisely align the pedestal in the horizontal direction. An electrostatic chuck is magnetically held to the pedestal.
US10854766B2
The present application relates to an encapsulant for a PV module, a method of manufacturing the same, and a PV module. The encapsulant according to an embodiment of the present application has excellent heat resistance or the like and improved creep properties, exhibits a haze with a certain level or less and excellent optical properties such as transparency or the like, when the encapsulant is applied to a PV module, physical properties such as durability, transparency, or the like are improved, and thus excellent generating efficiency of the PV module may be obtained.
US10854764B2
A solar cell includes a semiconductor substrate, a tunneling layer on one surface of the semiconductor substrate, a first conductive type area on the tunneling layer, a second conductive type area on the tunneling layer such that the second conductive type area is separated from the first conductive type area, and a barrier area interposed between the first conductive type area and the second conductive type area such that the barrier area separates the first conductive type area from the second conductive type area.
US10854761B1
A electrical switch has a first substrate, a first conducting layer disposed on the first substrate, a first dielectric layer disposed on the first conducting layer and a second conducting layer disposed on the first dielectric layer, and the second conducting layer disposed on the second substrate, and a conductive via connected to the first conducting layer and extending through the first dielectric layer. Active dielectric has a first conductor, a first dielectric layer disposed on the first conducting layer, one or more electrical switches disposed on the first dielectric layer, a dielectric layer disposed between neighboring electrical switches, the second dielectric layer disposed on the last electrical switch, and the second conducting layer disposed on the second dielectric layer.
US10854757B2
A transistor including a channel disposed between a source and a drain, a gate electrode disposed on the channel and surrounding the channel, wherein the source and the drain are formed in a body on a substrate and the channel is separated from the body. A method of forming an integrated circuit device including forming a trench in a dielectric layer on a substrate, the trench including dimensions for a transistor body including a width; forming a channel material in the trench; recessing the dielectric layer to expose a first portion of the channel material; increasing a width dimension of the exposed channel material; recessing the dielectric layer to expose a second portion of the channel material; removing the second portion of the channel material; and forming a gate stack on the first portion of the channel material, the gate stack including a gate dielectric and a gate electrode.
US10854741B2
An enhanced HFET, comprising a HFET device body. Regions without two-dimensional electron gas are provided on a channel layer (2) at the portion between a drain electrode (6) and a source electrode (4) of the HFET device body, and there is a region without two-dimensional electron gas provided on the channel layer (2) at the portions excluding the area under a gate electrode (5); two-dimensional electron gas regions are provided on the channel layer (2) excluding the portions located between the drain electrode (6) and the source electrode (4) and provided with the regions without two-dimensional electron gas; the channel layer (2) at the portion between the gate electrode (5) and the source electrode (4) and the portion between the gate electrode (5) and the drain electrode (6) are each provided with a two-dimensional electron gas region; and two-dimensional electron gas (8) is provided at a portion or whole portion of a two-dimensional electron gas layer at the channel layer (2) at the portion right under the gate electrode (5). The HFET has the advantages of high saturation current, high threshold voltage controllability, fast response, low energy consumption, and the like.
US10854739B2
A power semiconductor device includes: a drift region; a plurality of IGBT cells each having a plurality of trenches extending into the drift region along a vertical direction and laterally confining at least one active mesa which includes an upper section of the drift region; and an electrically floating barrier region of an opposite conductivity type as the drift region and spatially confined, in and against the vertical direction, by the drift region. A total volume of all active mesas is divided into first and second shares, the first share not laterally overlapping with the barrier region and the second share laterally overlapping with the barrier region. The first share carries the load current at least within a range of 0% to 100% of a nominal load current. The second share carries the load current if the load current exceeds at least 0.5% of the nominal load current.
US10854737B2
Techniques are disclosed for methods of post-treating an etch stop or a passivation layer in a thin film transistor to increase the stability behavior of the thin film transistor.
US10854728B2
According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.
US10854721B2
A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region.
US10854718B2
In one embodiment, a method of forming a HEM diode may comprise forming the HEM diode with high forward voltage that is greater than one of a gate-to-source threshold voltage of a HEMT or a forward voltage of a P-N diode.
US10854699B2
Discussed is an organic light emitting display device with auxiliary electrode and method of manufacturing the same according to the embodiments. The present disclosure is directed to provide a top emission type transparent organic light emitting display device and a method of manufacturing the same, which provides an area of an auxiliary electrode that effectively reduces a resistance of a cathode electrode, and decreases the number of masks, thereby simplifying the manufacturing process.
US10854688B2
A display panel includes a planarization layer, self-luminous elements, a first wiring line, a second wiring line, and a sensing wiring line. The first wiring line is coupled to the first electrode layer through a first opening of the planarization layer. The second wiring line is coupled to the second electrode layer through a second opening of the planarization layer. The sensing wiring line is provided in a region and is electrically separated from the first electrode layer, the second electrode layer, the first wiring line, and the second wiring line. The region is positioned in the same layer as the first electrode layer, in the same layer as the second wiring line, or in a layer disposed between the first electrode layer and the second wiring line, and is positioned between the first electrode layer and the second opening.
US10854683B2
A pixel arrangement structure of an OLED display is provided. The pixel arrangement structure includes: a first pixel having a center coinciding with a center of a virtual square; a second pixel separated from the first pixel and having a center at a first vertex of the virtual square; and a third pixel separated from the first pixel and the second pixel, and having a center at a second vertex neighboring the first vertex of the virtual square.
US10854675B2
The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.
US10854673B2
An elementary cell includes a non-volatile resistive random-access memory mounted in series with a volatile selector device, the memory including an upper electrode, a lower electrode and a layer made of a first active material, designated memory active layer. The selector device includes an upper electrode, a lower electrode and a layer made of a second active material, designated selector active layer. The cell includes a one-piece conductor element including a first branch having one face in contact with the lower surface of the memory active layer in order to form the lower electrode of the memory, a second branch having one face in contact with the upper surface of the selector active layer in order to form the lower electrode of the memory.
US10854668B2
A pixel including a workpiece having a protrusion and a bulk, wherein the protrusion extends from an upper surface of the bulk. The pixel further includes a floating diffusion node in the protrusion. The pixel further includes a photosensitive device in the bulk. The pixel further includes an isolation well surrounding the photosensitive device.
US10854666B2
A protective film composition includes a polymer having the following formula: each of a, b, and c is a mole fraction; a+b+c=1; 0.05≤a/(a+b+c)≤0.3; 0.1≤b/(a+b+c)≤0.6; 0.1≤c/(a+b+c)≤0.6; each of R1, R2, and R3 is a hydrogen atom or a methyl group; R4 is a hydrogen atom, a butyrolactonyl group, or a substituted or unsubstituted C3 to C30 alicyclic hydrocarbon group; and R5 is a substituted or unsubstituted C6 to C30 linear or cyclic hydrocarbon group. A method of manufacturing a semiconductor package includes forming a sawing protective film on a semiconductor structure by using the protective film composition and sawing the sawing protective film and the semiconductor structure from the sawing protective film.
US10854665B2
A semiconductor wafer has a plurality of non-rectangular semiconductor die with an image sensor region. The non-rectangular semiconductor die has a circular, elliptical, and shape with non-linear side edges form factor. The semiconductor wafer is singulated with plasma etching to separate the non-rectangular semiconductor die. A curved surface is formed in the image sensor region of the non-rectangular semiconductor die. The non-rectangular form factor effectively removes a portion of the base substrate material in a peripheral region of the semiconductor die to reduce stress concentration areas and neutralize buckling in the curved surface of the image sensor region. A plurality of openings or perforations can be formed in a peripheral region of a rectangular or non-rectangular semiconductor die to reduce stress concentration areas and neutralize buckling. A second semiconductor die can be formed in an area of the semiconductor wafer between the non-rectangular semiconductor die.
US10854664B2
The present disclosure relates to a solid-state image pickup device and a method for manufacturing the same, and an electronic apparatus, capable of suppressing color mixture, stray light, reduction in contour resolution, and the like. A solid-state image pickup device includes: a light shielding body having light shielding walls and a light transmitting portion formed in an opening portion between the light shielding walls; a first light shielding layer which is formed on an incident surface side of light of the light shielding body, and has an opening portion narrower than the opening portion of the light shielding body for each of the opening portions of the light shielding body; a microlens provided on the incident surface side of light of the light shielding body and for each of the opening portions of the first light shielding layer; a light receiving element layer in which a large number of light receiving elements which perform photoelectric conversion in accordance with incident light condensed by the microlens and input via the light transmitting portion of the light shielding body are arranged; and a second light shielding layer which is formed on the light receiving element layer side of the light shielding body, and has an opening portion narrower than the opening portion of the light shielding body and wider than the first light shielding layer for each of the opening portions of the light shielding body. The present disclosure can be used for a compound eye optical system, for example.
US10854661B2
Provided is a solid-state imaging device that includes: a first pixel provided with a color filter layer having a transmission band in a visible light wavelength region on a light-receiving surface of a first light-receiving element; a second pixel provided with an infrared pass filter layer having a transmission band in an infrared wavelength region on a light-receiving surface of a second light-receiving element; an infrared cut filter layer that is provided on a position overlapping with the color filter layer and transmits light in the visible light wavelength region by blocking light in the infrared wavelength region; and a cured film provided in contact with the infrared cut filter layer.
US10854660B2
The present disclosure relates to a solid-state image capturing element capable of suppressing a dark current, a manufacturing method thereof, and an electronic device. Provided is a solid-state image capturing element including: a photoelectric conversion unit formed outside a semiconductor substrate; and a charge retention section that is formed in the semiconductor substrate and retains charges generated in the photoelectric conversion unit. Among surfaces of the charge retention section, a bottom surface on a side opposite to a surface of a gate side of a transistor formed in the semiconductor substrate is covered by an insulation film. The present disclosure can be applied to, for example, solid-state image capturing elements and the like.
US10854658B2
An image sensor includes a photodiode within a semiconductor substrate and an interconnect structure over the semiconductor substrate. The interconnect structure includes a contact etch stop layer (CESL), a plurality of dielectric layers over the CESL and a plurality of metallization layers in the plurality of dielectric layers. At least one dielectric layer of the plurality of dielectric layers includes a low-k dielectric material. An opening is extended through the plurality of dielectric layers to expose a portion of the CESL above an active region of the photodiode. A cap layer is on sidewalls of the opening. The cap layer includes a dielectric material having a higher moisture resistance than the low-k dielectric material.
US10854657B2
The present technique relates to a solid-state image pickup element and an electronic apparatus each of which enables a pad to be formed in a shallow position while reduction of a quality of a back side illumination type solid-state image pickup element is suppressed. The solid-state image pickup element includes a pixel substrate in which a light condensing layer for condensing incident light on a photoelectric conversion element, a semiconductor layer in which the photoelectric conversion element is formed, and a wiring layer in which a wiring and a pad for outside connection are formed are laminated on one another, and at least a part of a first surface of the pad is exposed through a through hole completely extending through the light condensing layer and the semiconductor layer. The present technique, for example, can be applied to a back side illumination type CMOS image sensor.
US10854652B2
An array of diffraction-pattern generators employ phase anti-symmetric gratings to projects near-field spatial modulations onto a closely spaced array of photoelements. Each generator in the array of generators produces point-spread functions with spatial frequencies and orientations of interest. The generators are arranged in an irregular mosaic with little or no short-range repetition. Diverse generators are shaped and placed with some irregularity to reduce or eliminate spatially periodic replication of ambiguities to facilitate imaging of nearby scenes.
US10854648B2
An image sensor includes a sensor layer and at least one metal layer. The sensor layer includes a plurality of sensing elements arranged as a 2-dimensional array along a first direction and a second direction. Each of the at least one metal layer includes a plurality of metal wires configured to form a plurality of apertures for passing lights to the plurality of sensing elements. At least one of the plurality of metal wires forming the plurality of apertures is disposed along a third direction different from the first direction and the second direction.
US10854643B2
The present application discloses a display panel and a display apparatus. The display panel includes a substrate, and a plurality of first-layer conducting wires, where each of the first-layer conducting wires is disposed on the substrate, a polarizing color filter layer is disposed on the first-layer conducting wire and forms a color filter film with anisotropy, and the first-layer conducting wire is connected to a column data driver and a pixel driver of the display panel.
US10854641B2
An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 μm is 1 aA or less.
US10854631B2
A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.
US10854630B2
A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, a common source extension structure including a first semiconductor layer having an n-type conductivity and a gate insulating layer between the substrate and the channel structures, a plurality of gate electrodes on the common source extension structure and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension structure and including a second semiconductor layer having an n-type conductivity. An upper portion of the common source extension structure has a first width, and a lower portion of the common source extension structure has a second width smaller than the first width.
US10854629B2
An alternating stack of insulating layers and spacer material layers is formed over a substrate. A staircase region having stepped surfaces is formed by patterning the alternating stack. Memory opening fill structures are formed in a memory array region, and support pillar structures are formed in the staircase region. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. The support pillar structures include first support pillar structures and having a first maximum lateral dimension and second support pillar structures having a second maximum lateral dimension that is less than the first maximum lateral dimension and interlaced with the first support pillar structures. The sacrificial material layers are replaced with electrically conductive layers. The second support pillar structures are positioned interstitially among the first support pillar structures and contact via structures that are formed on the electrically conductive layers to provide additional structural support.
US10854624B2
Provided is a semiconductor memory device including a substrate, an isolation structure, a first gate dielectric layer, a first conductive layer, a second gate dielectric layer, a second conductive layer, and a protective layer. The substrate has an array region and a periphery region. The isolation structure is disposed in the substrate between the array and periphery regions. The first gate dielectric layer is disposed on the substrate in the array region. The first conductive layer is disposed on the first gate dielectric layer. The second gate dielectric layer is disposed on the substrate in the periphery region. The second conductive layer is disposed on the second dielectric layer. The second conductive layer extends to cover a portion of a top surface of the isolation structure. The protective layer is disposed between the second conductive layer and the isolation structure.
US10854622B2
A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.
US10854620B2
According to one embodiment, a semiconductor memory device includes: first interconnect layers; second interconnect layers; a first memory pillar extending through the first interconnect layers; a second memory pillar extending through the second interconnect layers; a first film provided above the first interconnect layers, having a planar shape corresponding to the first interconnect layers and extending in the first direction; and a second film provided above the second interconnect layers, separate from the first film in the second direction, having a planar shape corresponding to the second interconnect layers and extending in the first direction. The first and second films have a compressive stress higher than a silicon oxide film.
US10854618B2
A memory device includes: a conductive layer coupled to a reference voltage level; a first storage portion vertically coupled to a first surface of the conductive layer; and a second storage portion vertically coupled to a second surface of the conductive layer; wherein the second surface is opposite to the first surface.
US10854616B2
Reference marks for forming a staircase structure are disposed along slit areas of a 3D memory structure, and slits of the 3D memory structure are formed on the slit areas. In a staircase area, the reference marks are formed by etching the topmost one of stacked layers, having a pair of a dielectric layer and a sacrificial layer, in a stacked structure.
US10854614B2
Disclosed are semiconductor devices and methods of manufacturing the same. A support layer and a mold layer are partially etched off from the substrate, to form a mold pattern and a support pattern on the substrate such that a contact hole is formed through the support pattern and the mold pattern and an interconnector is exposed therethrough. A lower electrode layer is formed on the mask pattern to fill the contact hole, and a lower electrode is formed in the contact hole by partially removing the lower electrode layer and the mask pattern. The lower electrode is contact with the interconnector and is supported by the support pattern having the same thickness as the support layer.
US10854611B2
Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.
US10854588B2
A semiconductor device includes a normally-on junction FET having a first gate electrode, a first source electrode and a first drain electrode, a normally-off MOSFET having a second gate electrode, a second source electrode and a second drain electrode, and a voltage applying unit which applies a voltage to the first gate electrode. The first source electrode of the junction FET is electrically connected to the second drain electrode of the MOSFET, and the junction FET is thus connected to the MOSFET in series, and the voltage applying unit applies a second voltage with a polarity opposite to that of a first voltage applied to the first gate electrode when the junction FET is brought into an off-state, to the first gate electrode when the MOSFET is in an on-state.
US10854582B2
Disclosed is a light-emitting module including: a first insulation film having light transmissive property; a conductor layer provided on the first insulation film; a second insulation film disposed to face the first insulation film; a plurality of light-emitting elements interposed between the first insulation film and the second insulation film and have one surface on which a pair of electrodes connected to the conductor layer are provided; and a board that is connected to the first insulation film and has a circuit connected to the conductor layer.
US10854580B2
The present disclosure provides a semiconductor structure including a first chip having a first dielectric surface, a second chip having a second dielectric surface facing the first dielectric surface and maintaining a distance thereto, and an air gap between the second dielectric surface and the first dielectric surface. The first chip includes a plurality of first conductive lines in proximity to the first dielectric surface and parallel to each other, two adjacent first conductive lines each having a sidewall partially exposed from the first dielectric surface. The present disclosure further provides a method for manufacturing the semiconductor structure described herein.
US10854579B2
The present disclosure provides a semiconductor package, including a substrate having a first surface and a second surface opposite to the first surface, a semiconductor die connected to the first surface of the substrate, and a conductive bump connected to the conductive via at the second surface. The substrate includes a conductive line surrounded by a dielectric and a conductive via connected to the conductive line and penetrating the dielectric at the second surface.
US10854575B2
The present invention discloses a three-dimensional package structure which can achieve a relatively high utilization of an internal space thereof, so that a size of electronic package structure can be reduced. The three-dimensional package structure comprises a first electronic component, a plurality of second electronic components and a plurality of conductive patterns. The first electronic component has a top surface and a bottom surface. The plurality of second electronic components are disposed over the top surface of the first electronic component. The plurality of conductive patterns are disposed over the plurality of second electronic components to electrically connect the plurality of second electronic components and the first electronic component.
US10854570B2
A method of fabricating an integrated fan-out package is provided. The method includes the following steps. An integrated circuit component is provided on a substrate. An insulating encapsulation is formed on the substrate to encapsulate sidewalls of the integrated circuit component. A redistribution circuit structure is formed along a build-up direction on the integrated circuit component and the insulating encapsulation. The formation of the redistribution circuit structure includes the following steps. A dielectric layer and a plurality of conductive vias embedded in the dielectric layer are formed, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction. A plurality of conductive wirings is formed on the plurality of conductive vias and the dielectric layer. An integrated fan-out package of the same is also provided.
US10854566B2
A pre-conductive array disposed on a target circuit substrate comprises a plurality of conductive electrode groups disposed on the target circuit substrate, and at least a conductive particle dispose on each of conductive electrodes of a part or all of the conductive electrode groups. The at least a conductive particle and the corresponding conductive electrode form a pre-conductive structure, and the pre-conductive structures form the pre-conductive array.
US10854563B2
A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.
US10854561B2
A semiconductor package includes: a connection member including a plurality of connection pads and a redistribution layer; a semiconductor chip disposed on the connection member; an encapsulant sealing the semiconductor chip; a passivation layer disposed on the connection member; a plurality of under bump metallurgy (UBM) pads disposed on the passivation layer; and a plurality of UBM vias connecting the plurality of UBM pads to the plurality of connection pads, respectively, wherein the plurality of UBM pads include a first UBM pad overlapped with the semiconductor chip in a stacking direction, and a second UBM pad located outside of the overlapped region, and the first connection pad has an area larger than an area of an associated first UBM pad while the associated first UBM pad is overlapped in the stacking direction, and has an area larger than an area of the second connection pad.
US10854560B2
A semiconductor device includes: an island that is formed by a metallic layer including a single metallic layer or a plurality of different metallic layers; a semiconductor chip provided upon an upper surface of the island, and having a pair of side portions mutually opposing each other; a plurality of signal terminals disposed at an external periphery of at least the pair of side portions of the semiconductor chip, and formed by the metallic layer; a grounding terminal disposed at an external periphery of the plurality of signal terminals, and formed by the metallic layer; electrically conductive connection members that are connected between each of a plurality of electrodes of the semiconductor chip and each of the plurality of signal terminals; sealing resin that seals the island, the semiconductor chip, the electrically conductive connection members, the plurality of signal terminals, and the grounding terminal, so that a lower surface of the island, lower surfaces of the plurality of signal terminals, and a lower surface of the grounding terminal are exposed to the exterior; and a metallic shielding layer that covers over an outer peripheral side surface and an upper surface of the sealing resin, and a portion of the grounding terminal.
US10854559B2
Devices and methods are disclosed, related to shielding and packaging of radio-frequency (RF) devices on substrates. In some embodiments, a method for providing electro-magnetic interference shielding for a radio-frequency module can include applying a metal-based covering over a portion of a lead-frame package, the package having a plurality of pins with at least one pin exposed from overmold compound and in contact with the metal-based covering. The method can also include mounting the lead-frame package on a substrate. The method can further include connecting the metal-based covering to a ground plane of the substrate.
US10854544B2
Anti-fuse structure circuit and method of forming an anti-fuse structure circuit are provided. A substrate is provided, and an anti-fuse is formed on the substrate by forming a first gate structure and a dielectric layer on the substrate and forming conductive plugs respectively in the dielectric layer at two sides of the first gate structure. The dielectric layer covers the first gate structure, and the conductive plugs have a width decreasing from top to bottom. A second gate structure is formed on the substrate. A top surface of the first gate structure is higher than a top surface of the second gate structure. The dielectric layer also covers the second gate structure. The conductive plugs are also located respectively in the dielectric layer at two sides of the second gate structure.
US10854543B2
A semiconductor device includes: a substrate; a first wiring layer arranged above the substrate; a first insulating film covering the first wiring layer; a lower oxidation preventing film arranged on the first insulating film; at least one thin-film resistor arranged on the lower oxidation preventing film; an upper oxidation preventing film arranged on the at least one thin-film resistor; a second insulating film covering the lower oxidation preventing film, the at least one thin-film resistor, and the upper oxidation preventing film; a second wiring layer arranged on the second insulating film; and a third insulating film covering the second wiring layer. The first wiring layer overlaps an end portion of the at least one thin-film resistor when viewed in a normal direction of one surface of the substrate.
US10854536B2
A fingerprint chip package and method for processing same, relating to a field of biometric identification. The fingerprint chip package includes: a lead frame (1), a chip (2), and a plastic packaging part enclosing the lead frame (1) and the chip (2); the lead frame (1) comprises a base island (13), a connecting rib (11), and a golden finger (12); the base island (13) is used for bearing the chip (2); the connecting rib (11) is used for supporting the lead frame (1) and connecting the base island (13) via the golden finger (12); and the golden finger (12) is used for fixing the base island (13) and electrically connecting with the chip (2).
US10854529B2
A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.
US10854526B2
Embodiments of the present application provide the chip packaging structure, the chip module and the electronic terminal. In the chip packaging structure, the chip is accommodated in the trench of the substrate to decrease the thickness and volume of the chip packaging structure; and the plastic package is provided on the surface of the substrate on which the chip is disposed to plastically package the chip, which not only ensures the structural strength of the chip packaging structure, but also reduces the warpage that may be caused due to the decrease of the thickness of the chip packaging structure as much as possible. In addition, the surface of the plastic package is treated to be a flat surface, such that the chip module has good flatness and the adaptability of the chip module is improved.
US10854517B2
Methods of manufacturing a semiconductor chip are provided. The methods may include providing a semiconductor substrate including integrated circuit regions and a cut region. The cut region may be between the integrated circuit regions. The methods may also include forming a modified layer by emitting a laser beam into the semiconductor substrate along the cut region, polishing an inactive surface of the semiconductor substrate to propagate a crack from the modified layer, and separating the integrated circuit regions along the crack. The cut region may include a plurality of multilayer metal patterns on an active surface of the semiconductor substrate, which is opposite to the inactive surface of the semiconductor substrate. The plurality of multilayer metal patterns may form a pyramid structure when viewed in cross section.
US10854512B2
The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having active regions, conductive contact features landing on the active regions, and a conductive via feature to be landing on a first subset of the conductive contact features and to be spaced from a second subset of the conductive contact features; evaluating a spatial parameter of the conductive via feature to the conductive contact features; and modifying the IC layout according to the spatial parameter such that the conductive via feature has a S-curved shape.
US10854510B2
Aspects of the present invention relate to approaches for forming a narrow source-drain contact in a semiconductor device. A contact trench can be etched to a source-drain region of the semiconductor device. A titanium liner can be deposited in this contact trench such that it covers substantially an entirety of the bottom and walls of the contact trench. An x-metal layer can be deposited over the titanium liner on the bottom of the contact trench. A titanium nitride liner can then be formed on the walls of the contact trench. The x-metal layer prevents the nitriding of the titanium liner on the bottom of the contact trench during the formation of the nitride liner.
US10854498B2
A wafer-supporting device for supporting a wafer thereon adapted to be installed in a semiconductor-processing apparatus includes: a base surface; and protrusions protruding from the base surface and having rounded tips for supporting a wafer thereon. The rounded tips are such that a reverse side of a wafer is supported entirely by the rounded tips by point contact. The protrusions are disposed substantially uniformly on an area of the base surface over which a wafer is placed, wherein the number (N) and the height (H [μm]) of the protrusions as determined in use satisfy the following inequities per area for a 300-mm wafer: (−0.5N+40)≤H≤53;5≤N≤100.
US10854495B2
A pressure sensitive adhesive tape for semiconductor processing includes a base having a Young's modulus of 1000 MPa or more at 23° C., and a pressure sensitive adhesive layer provided on at least one surface of the base, and the product (N)×(C) of (N) and (C) is 500 or more at 30° C., and 9000 or less at 60° C., where (N) [μm] is a thickness of the pressure sensitive adhesive layer and (C) [μm] is a creep amount.
US10854487B2
The invention relates to a method for the transportation and/or storage of at least one semiconductor plate, in which the plate is disposed in a hermetic container (1) filled with hydrogen at a pressure of between 10−1 and 4*103 Pa and, optionally, at least one inert gas, the total pressure in the casing being between 10−1 and 5*104 Pa.
US10854482B2
A reaction chamber is provided. The reaction chamber includes a chamber body, a dielectric window, and a power supplier. The dielectric window is provided on top of the chamber body along a first direction and hermetically connected with the chamber body. Each coil of a plurality of sets of coils is wound around an outer surface of the dielectric window at an interval along the first direction. The plurality of sets of coils are connected in parallel, with first ends electrically coupled to the power supplier for supplying power to each set of the plurality of sets of coils, and with second ends grounded. The second ends of the plurality of sets of coils are arranged in proximity between the first ends.
US10854481B2
A substrate processing method includes holding a substrate horizontally, supplying water-containing processing liquid to an upper surface of the substrate, forming a low surface tension liquid film, covering the upper surface by supplying that liquid to the substrate's upper surface, supplying a gas to a center region of the liquid film to form an opening in the center, widening the opening in order to remove the film, rotating the substrate around a predetermined rotational axis along a vertical direction, blowing, in the opening widening step, the gas toward a gas supply position that is set further inward than a peripheral edge of the opening on the upper surface of the substrate, and moving the gas supply position toward the peripheral edge of the upper surface of the substrate, and supplying, the low surface tension liquid toward a liquid landing position that is set further outward and moving the liquid landing position toward the peripheral edge of the upper surface of the substrate.
US10854475B2
A wiring substrate includes: a first insulating layer; a plurality of wiring patterns formed on one surface of the first insulating layer; a dummy pattern formed, on the one surface of the first insulating layer, between the nearby wiring patterns; and a second insulating layer made of resin and formed on the one surface of the first insulating layer so as to cover the nearby wiring patterns and the dummy pattern, wherein the dummy pattern is a dot pattern arranged at a center portion between the nearby wiring patterns, and wherein a height of at least one dot constituting the dummy pattern is lower than heights of the nearby wiring patterns.
US10854469B2
When a silicon concentration of a phosphoric acid aqueous solution inside a tank reaches an upper limit value of a specified concentration range, the phosphoric acid aqueous solution is drawn off from the tank and/or an amount of the phosphoric acid aqueous solution returning to the tank is decreased to decrease a liquid amount inside the tank to a value not more than a lower limit value of a specified liquid amount range. When the liquid amount inside the tank decreases to the value not more than the lower limit value of the specified liquid amount range, the phosphoric acid aqueous solution is replenished to the tank to increase the liquid amount inside the tank to a value within the specified liquid amount range and decrease the silicon concentration of the phosphoric acid aqueous solution inside the tank to a value within the specified concentration range.
US10854464B2
A manufacturing process of an elemental chip includes steps of preparing a substrate held on the holding tape, the substrate including first and second sides opposite each other and the second side thereof being held on the holding tape, and the substrate further including a plurality of element regions and a plurality of segmentation regions defining each of the element regions; setting a nozzle to have a length between a lower most edge of the nozzle and the first side of the substrate in a range between 20 mm and 150 mm, spraying a resist solution to form droplets of the resist solution, the resist solution containing a resist constituent and a solvent; forming a resist layer by vaporizing the solvent from the droplets and depositing the resist constituent on the first side of the substrate that is held on the holding tape such that an amount of the solvent remained in the resist layer to be in a range between 5 wt. % and 20 wt. %; patterning the resist layer to expose the first side of the substrate in the segmentation regions; and plasma-etching the first side of the substrate exposed in the segmentation regions thereof.
US10854453B2
A substrate processing technique is described herein for etching layers, such as dielectric layers, and more particularly low k dielectric layers in a manner that minimizes etch lag effects. Multiple etch processes are utilized. A first etch process may exhibit etch lag. A second etch process is a multi-step process that may include a deposition sub-step, a purge sub-step and an etch sub-step. The second etch process may exhibit inverse etch lag. The second etch process may be a cyclic process which performs the deposition, purge and etch sub-steps a plurality of times. The second etch process may be an atomic layer etch based process, and more particularly a quasi-atomic layer etch. The combination of the first etch process and the second etch process may provide the desired net effect for the overall etch lag when etching the dielectric layer.
US10854452B2
A method of manufacturing a semiconductor device includes forming first sacrificial cores on a first region of a lower structure and second sacrificial cores on a second region of the lower structure, forming spacers on side walls of the first sacrificial cores and side walls of the second sacrificial cores, forming a protective pattern covering the second sacrificial cores on the second region of the lower structure, removing the first sacrificial cores from the first region, and etching the lower structure using the spacers on the first region, and the second sacrificial cores and the spacers on the second region. By using only spacers as an etching mask in the first region and the sacrificial cores with the spacers as an etching mask in the second region, patterns with different widths are formed simultaneously on the first and second regions.
US10854446B2
Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.
US10854442B2
An orientation chamber of a semiconductor substrate processing system is provided. The orientation chamber includes a substrate holder, an orientation detector, and a purging system. The substrate holder is configured to hold a substrate. The orientation detector is configured to detect the orientation of the substrate. The purging system is configured to inject a cleaning gas into the orientation chamber and remove contaminants from the substrate.
US10854438B2
In an inductively coupled plasma-mass spectrometry (ICP-MS) system, ions are transmitted into a collision/reaction cell. A DC potential is applied at an exit of the cell at a first magnitude to generate a DC potential barrier effective to prevent the ions from exiting the cell. The DC potential barrier is maintained during a confinement period to perform an interaction. After the confinement period, analyte ions or product ions are transmitted to a mass spectrometer by switching the exit DC potential to a second magnitude effective to allow the analyte ions or product ions to pass through the cell exit as a pulse. The analyte ions or product ions are then counted during a measurement period. The interaction may be ion-molecule reactions or ion-molecule collisions.
US10854435B2
Sb—Te-based alloy sintered sputtering target having a Sb content of 10 to 60 at %, a Te content of 20 to 60 at %, and remainder being one or more types of elements selected from Ag, In, and Ge and unavoidable impurities, wherein an average grain size of oxides is 0.5 μm or less. An object of this invention is to improve the texture of the Sb—Te-based alloy sintered sputtering target in order to prevent the generation of arcing during sputtering and improve the thermal stability of the sputtered film.
US10854432B2
The present disclosure generally relates to methods and apparatus for facilitating electrical feedthrough in plasma processing chambers. The apparatus includes an electrically insulating housing positioned on a backside of the substrate support to contain a secondary plasma therein. The secondary plasma facilitates an electrical connection between the substrate support and electrical power or ground located outside the processing chamber. The methods include utilizing a secondary plasma to electrically couple substrate support to and electrical power or ground located outside the processing chamber.
US10854428B2
Apparatus and methods of processing a substrate in a plasma enhanced spatial atomic layer deposition chamber. A substrate is moved through one or more plasma processing regions and one or more non-plasma processing regions while the plasma power is pulsed to prevent a voltage differential on the substrate from exceeding a breakdown voltage of the substrate or device being formed on the substrate.
US10854421B2
A charged particle beam system includes a charged particle source, an extraction electrode, a suppressor electrode, a first variable voltage supply for biasing the extraction electrode with an extraction voltage and a second variable voltage supply for biasing the suppressor electrode with a suppressor voltage.
US10854419B2
According to one embodiment, a contour extraction method for extracting a contour of a target object from an image obtained using an electron beam includes: extracting the contour of the target object from a backscattered electron image; creating a dictionary for associating a secondary electron image obtained from a portion common to the backscattered electron image with the contour; calculating a likelihood of the contour of the target object in a plurality of positions of a newly obtained secondary electron image by referencing the dictionary regarding the newly obtained secondary electron image; and setting a route along which a total sum of the likelihood is maximized out of the plurality of positions as the contour of the target object.
US10854418B2
A mass analyzer includes a mass analyzing magnet that applies a magnetic field to ions extracted from an ion source to deflect the ions, a mass analyzing slit that is provided downstream of the mass analyzing magnet and allows an ion of a desired ion species among the deflected ions to selectively pass, and a lens device that is provided between the mass analyzing magnet and the mass analyzing slit and applies a magnetic field and/or an electric field to the ion beam to adjust the convergence or divergence of a ion beam. The mass analyzer changes a focal point of the ion beam in a predetermined adjustable range between an upstream side and a downstream side of the mass analyzing slit with the lens device to adjust mass resolution.
US10854415B1
A fuse includes a tubular body having two ends each having a first cap, which is formed with a through hole; a fusible and breakable unit including a first fusible filament arranged inside the tubular body and having two ends extending outward through the through holes respectively; and a plurality of second caps each of which has a surface that is formed with a recessed part and an opposite surface that is provided with a conductive wire. The recessed parts of the second caps are mounted to outer circumferences of the first caps. The two ends of the first fusible filament are respectively coupled between the first caps and the second caps corresponding thereto so as to extend a distance between the two ends of the first fusible filament and thus, preventing the occurrences of electrical arc after the first fusible filament is fused and broken.
US10854414B2
A compact disconnect device includes a magnetic arc deflection assembly including at least one set of stacked arc plates and at least one magnet disposed adjacent switchable contacts and establishing a magnetic field across the stacked arc plates. The magnetic arc deflection assembly facilitates reliable connection and disconnection of DC voltage circuitry well above 125 VDC with reduced arcing intensity and duration. The disconnect device may be a compact fusible disconnect switch device having dual sets of switch contacts in the same current path.
US10854411B2
A microelectromechanical systems (MEMS) switching circuit and related apparatus is provided. A MEMS apparatus includes a MEMS switching circuit and a control circuit. The MEMS switching circuit includes a first number of MEMS switches, each configured to close and open based on a high driving voltage and a low driving voltage, respectively. The MEMS switching circuit includes a MEMS-based driver circuit configured to receive a second number of control signals that collectively identify a selected MEMS switch among the first number of MEMS switches. Accordingly, the MEMS-based driver circuit decodes the second number of control signals and causes the selected MEMS switch to close. By using a lesser number of control signals to control a larger number of MEMS switches, it may be possible to reduce control lines between the control circuit and the MEMS switching circuit, thus helping to reduce routing complexity and footprint of the MEMS apparatus.
US10854409B2
An electromagnetic relay includes a movable terminal including a movable contact, a fixed terminal including a fixed contact that faces the movable contact, first irons disposed on one of the fixed terminal and the movable terminal, and a second iron disposed on another one of the fixed terminal and the movable terminal such that the second iron at least partially overlaps both of the first irons.
US10854408B2
A magnetic flux assembly for closing a magnetic circuit of a relay and a relay. The magnetic flux assembly has a yoke and a U-shaped armature that is movable relative to the yoke. The yoke has a coil part that is in a coil and a flux conduction part that conducts the magnetic flux generated by the coil.
US10854402B2
A knob assembly includes a lower housing, a pushing member, an upper housing, and a screw member. The lower housing includes a tank and hook structures. A through via is formed at the center of the lower housing. The upper housing is rotatably stacked on the lower housing. A lower surface of the upper housing includes an annular hook groove. The pushing member is disposed between the upper and the lower housing, and includes a body and pushing structures. A screw hole is formed at the center of the body. When the screw member is screwed into the screw hole through the through via, the pushing member moves toward and locks the lower housing, and the pushing structures push the hook structures to cause the hook structures to expand outward and be hooked to the annular hook groove, so that the upper housing is limited by the lower housing.
US10854397B2
An electric machine, to a motor vehicle with such an electric machine, and to a method for operating such an electric machine. The electric machine includes at least one sliding contact which is formed by a slip ring connected to a rotor and by at least one brush and via which an operating current flows during an operation of the electric machine. A control unit is configured to control the operation of the electric machine. The control unit is configured to verify a predetermined operating criterion of the electric machine and, if said operating criterion is met, to inject a cleaning current according to a predetermined scheme, which then flows independently of the operating current via the sliding contact and cleans said sliding contact in order to maintain or improve a current transfer capability of the sliding contact.
US10854396B2
A packaging material for electrochemical cells, which has insulating properties sufficient for preventing a short circuit, while exhibiting excellent electrolyte solution resistance and water vapor barrier properties. A packaging material for electrochemical cells is obtained by sequentially laminating a metal layer, an adhesive resin layer and a thermally adhesive resin layer in this order, wherein: a base coating layer is provided between the metal layer and the adhesive resin layer; and the base coating layer contains at least a zirconium oxide (A) having an average particle diameter within the range of from 1 nm to 500 nm (inclusive), one or more phosphorus-containing compounds (B) selected from the group of phosphorus compounds having 4 or more phosphonic groups in each molecule, and an acid-modified polyolefin resin (C).
US10854392B2
A multi-layer ceramic electronic component includes: a ceramic body including internal electrodes laminated in a first direction, a first main surface including a first flat region facing in the first direction, and a second main surface including a second flat region facing in the first direction; and a pair of external electrodes connected to the internal electrodes and facing each other in a second direction orthogonal to the first direction, a dimension of the ceramic body in the first direction being 1.1 times or more and 1.6 times or less a dimension of the ceramic body in a third direction orthogonal to the first and second directions, the first flat region being formed at a center portion of the first main surface in the second direction, the second flat region being formed at a center portion of the second main surface in the third direction.
US10854391B2
A multilayer capacitor includes a capacitor body including an active region, and upper and lower cover regions disposed on upper and lower portions of the active region, respectively. First and second external electrode are disposed on both ends of the capacitor body, respectively. The active region includes a plurality of first dielectric layers, first and second internal electrodes alternately disposed with the first dielectric layer interposed therebetween, and first and second auxiliary electrodes disposed on the first dielectric layers on which the first and second internal electrodes are disposed, respectively. The upper and lower cover regions each include a plurality of second dielectric layers having a thickness less than that of each of the first dielectric layers, and a dummy electrode disposed on the second dielectric layers.
US10854387B2
A capacitor component includes a capacitor component includes a body including a dielectric layer and first and second internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween, and first and second external electrodes disposed on the body and electrically connected to the first and second internal electrodes. The body may include a capacitance forming portion including the first and second internal electrodes, cover portions disposed on upper and lower surfaces of the capacitance forming portion, and margin portions disposed on side surfaces of the capacitance forming portion, in which the margin portions have a hardness ranging from 8.5 GPa to 14 GPa.
US10854385B2
A method for producing a ceramic substrate that includes a substrate body having ceramic layers and columnar projecting electrodes on a first primary surface of the substrate body. The method includes a step of preparing electrode formation sheets for forming the projecting electrodes, a step of perforating the electrode formation sheets with through holes and filling the through holes with a first electrically conductive paste containing a first electrically conductive powder, a step of building a composite multilayer body by stacking ceramic green sheets and the electrode formation sheets on a first primary surface of the stack of ceramic green sheets. The first electrically conductive powder contains electrically conductive metal(s) and anti-sintering ceramic(s) that controls the sintering of particles of the electrically conductive metal(s), with at least part of the surface of the particles of the electrically conductive metal(s) covered with the anti-sintering ceramic(s).
US10854376B2
A coil component includes a coil and a composite magnetic material containing magnetic particles. The magnetic particles have an average minor-axis length of more than 5.0 nm and 50 nm or less and an average aspect ratio of 2.0 or more and 10.0 or less. The magnetic particles are orientated substantially perpendicularly to a central axis of the coil and are orientated randomly within a perpendicular plane to the central axis of the coil. The composite magnetic material has a saturation magnetization σs of 80.0 emu/g or more.
US10854370B2
An embedded coil assembly embodiment includes a ferrite ring having an annular axis. The ferrite ring is positioned on a conductive metal surface. A plurality of separate, spaced apart conductive structures extend over the ferrite ring and are attached to the conductive metal surface in a first region of the conductive surface positioned radially outwardly of the annular axis of the ferrite ring and in a second region of the conductive surface positioned radially inwardly of the annular axis of the ferrite ring. An encapsulation layer covers, the ferrite ring and at least a portion of the plurality of conductive structures.
US10854369B2
A transformer station, in particular, an offshore transformer station including at least one transformer and at least one transformer cooling unit arranged on at least one side wall of the transformer station or a roof of the transformer station and configured to cool the at least one transformer. The transformer station also includes at least one air deflecting unit arranged on at least one roof edge of the transformer station and/or at least one air deflecting unit arranged on at least one side edge of the transformer station. The air deflecting unit is arranged such that an air movement is deflectable in the direction of the transformer cooling unit.
US10854348B2
An X-ray generator includes: a line X-ray source; a multilayer film mirror; and a side-by-side reflecting mirror including two concave mirrors joined together so as to share a join line. A cross section of a reflecting surface of the multilayer film mirror has a parabolic shape, and a focus of the parabolic shape is located at the line X-ray source. Cross sections of reflecting surfaces of the two concave mirrors of the side-by-side reflecting mirror each have a parabolic shape, and each of focuses of the parabolic shapes is located on a side opposite to the multilayer film mirror. An extended line of the join line of the side-by-side reflecting mirror passes through the multilayer film mirror and the line X-ray source as viewed in a plan view.
US10854343B2
The present invention relates to a nuclear reactor, more precisely a passive safety device applicable to a thermal neutron reactor and a nuclear fuel assembly equipped with the same. The nuclear fuel assembly for a thermal neutron reactor of the present invention includes multiple fuel rods; multiple guide thimbles arranged between the fuel rods; and a passive safety device including neutron absorber parts which are inserted in one or more guide thimbles.
US10854336B1
A system for customizing informed advisor pairings, the system including a computing device. The computing device is configured to identify a user feature wherein the user feature contains a user biological extraction. The computing device is configured to generate using element training data and using a first machine-learning algorithm a first machine-learning model that outputs advisor elements. The computing device receives an informed advisor element relating to an informed advisor. The computing device determines using output advisor elements whether an informed advisor is compatible for a user.
US10854333B2
A method and system for setting time blocks of a repeating time period is disclosed. The method and system may be a part of a healthcare management software system.
US10854330B1
Provided are mechanisms and processes for a medical appointment delay management system. According to various examples, the system includes a location sensor that detects when a medical professional wearing a personal beacon enters an examination room to conduct an examination of a particular patient. The system also includes a medical schedule processor that logs a time associated with when the medical professional enters the examination room and compares this time with scheduling information to predict whether future appointments in the schedule will be delayed. A notification interface, included in the system, is designed to notify an upcoming patient if their scheduled appointment will be substantially delayed. Scheduling information is cryptographically separated from HIPAA information.
US10854320B2
The disclosure includes a method and system for initiating at least one workflow associated with a patient, the system enabling users to create electronic messages, the method comprising the steps of presenting an electronic message via a display wherein the electronic message includes at least fields, associating the displayed electronic message with a first patient, receiving a general event descriptor entered by a system user via an interface in one of the message fields where the general event descriptor can be used to identify at least one workflow being requested by the user, obtaining the general event descriptor from the field, identifying a workflow associated with the general event descriptor and associated with the first patient and transmitting an electronic message to at least one entity that is capable of handling the workflow being requested by the user.
US10854318B2
Inferring a characteristic of an individual is disclosed. An indication that a first user and a second user have at least one shared chromosomal segment is received. Information about the second user is obtained. A characteristic of the first user is inferred based at least in part on the information about the second user.
US10854314B2
A representation of a nucleic acid sequence encodes a particular gene having at least one intron. An intron signature value corresponding to the at least one intron is determined based on a first computational function applied to at least one portion of the representation of the nucleic acid sequence corresponding to the at least one intron. A protein signature value is determined, being based on a second computational function applied to a representation of a protein. In a database, an association is formed between the intron and protein signature values. This process is repeated for each of a plurality of nucleic acid sequences. Nucleic acid sequences in the database are ordered based on a sort of corresponding intron signature values. An ordering determined by the sort is used to determine or confirm a role or function of a portion of a given nucleic acid sequence.
US10854305B2
An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator is readable. Responsive to determining that the status indicator readable, it can be determined that programming of data to the data block of the memory component did complete and there is a data retention loss.
US10854299B2
A data erase operation is performed on the memory system. The directed data erase operation performed on the memory system erases blocks of the memory device including blocks that are indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as valid without erasing those groups of memory cells (e.g., blocks) indicated as invalid. In some embodiments, a data erase operation that can be performed on a memory system may obtain information associated with failing scenes of groups of memory cells (e.g., blocks) prior to obtaining the information, and erase the blocks (e.g., invalid blocks) subsequently.
US10854298B2
A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
US10854295B2
Methods of operating an integrated circuit device, and integrated circuit devices configured to perform methods, including applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer, determining whether the I/O buffer is deemed to exhibit offset, and applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset.
US10854286B2
Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.
US10854285B2
A method for performing memory access includes: performing a first sensing operation corresponding to a first sensing voltage and performing at least a second sensing operation corresponding to a second sensing voltage to respectively generate a first digital value of a Flash cell of a Flash memory and a second digital value of the Flash cell of the Flash memory; using the first digital value, the second digital value, and charge distribution statistics information of the Flash memory to obtain soft information of a bit stored in the Flash cell, wherein the soft information corresponds to a threshold voltage of the Flash cell; and using the soft information to perform soft decoding.
US10854282B2
In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.
US10854279B2
A SRAM array is provided, including a first bit cell array and a second bit cell array arranged along a first direction; a strap cell arranged in a second direction and positioned between the first bit cell array and the second bit cell array along the first direction. The strap cell includes a first strap column, a second strap column, a doped P-type region, a doped N-type region, and a deep N-type well region. The first strap column includes a first P-type well region and two first N-type well regions adjacent opposite sides of the first P-type well region along the first direction. The second strap column is adjacent to the first strap column along the second direction. The second strap column includes a second N-type well region and two second P-type well regions adjacent opposite sides of the second N-type well region along the first direction.
US10854276B2
Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.
US10854269B2
The present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material. The array can include a plurality of access transistors comprising a first semiconductor material. A compute component can be formed over and coupled to the array. The compute component can include a plurality of compute transistors comprising a second semiconductor material. The second semiconductor material can have a higher concentration of doping ions than the first semiconductor material.
US10854264B2
Various implementations described herein refer to an integrated circuit having a sense amplifier that operates with a clock signal, and the sense amplifier may be biased with a bias signal that affects duration of the clock signal. The integrated circuit may include a delay circuit coupled to the sense amplifier, and the delay circuit may turn-off the clock signal. The delay circuit may have a current-starved delay stage that receives an input signal having a falling edge and provides a current-starved delay signal biased by the bias signal that also biases the sense amplifier.
US10854262B2
A memory device includes a first memory cell that is connected with a first source line, a first word line, and a first bit line, a first write circuit to receive first write data that are stored in the first memory cell through a first write input/output line and to control a voltage of the first source line and a voltage of the first bit line based on the first write data, and a first pull-down circuit to receive first pull-down data corresponding to the first write data from the first write circuit through a first internal metal line and to pulls down the voltage of at least one of the first source line and the first bit line to a predetermined voltage based on the first pull-down data.
US10854257B2
A magnetic device may include a layer stack. The layer stack may include a first ferromagnetic layer; a non-magnetic spacer layer on the first ferromagnetic layer, where the non-magnetic spacer layer comprises at least one of Ru, Ir, Ta, Cr, W, Mo, Re, Hf, Zr, or V; a second ferromagnetic layer on the non-magnetic spacer layer; and an oxide layer on the second ferromagnetic layer. The magnetic device also may include a voltage source configured to apply a bias voltage across the layer stack to cause switching of a magnetic orientation of the second ferromagnetic layer without application of an external magnetic field or a current. A thickness and composition of the non-magnetic spacer layer may be selected to enable a switching direction of the magnetic orientation of the second ferromagnetic layer to be controlled by a sign of the bias voltage.
US10854256B2
A storage element includes a layer structure including a storage layer having a direction of magnetization which changes according to information, a magnetization fixed layer having a fixed direction of magnetization, and an intermediate layer disposed therebetween, which intermediate layer contains a nonmagnetic material. The magnetization fixed layer has at least two ferromagnetic layers having a direction of magnetization tilted from a direction perpendicular to a film surface, which are laminated and magnetically coupled interposing a coupling layer therebetween. This configuration may effectively prevent divergence of magnetization reversal time due to directions of magnetization of the storage layer and the magnetization fixed layer being substantially parallel or antiparallel, reduce write errors, and enable writing operation in a short time.
US10854241B2
A method is disclosed in which first payload data included in a first file container and second payload data included in a second file container are determined. The first payload data is decoded to determine first un-encoded data representing first content, and the second payload data is decoded to determine second un-encoded data representing second content. At least one difference is determined between the first un-encoded data and the second un-encoded data, and third un-encoded data corresponding to the at least one difference is determined. The third un-encoded data is encoded to generate third payload data representing third content, and a third file container is generated that includes the third payload data.
US10854239B1
Data set groups are determined, wherein each data set group includes a plurality of data sets and each data set includes error-correcting information for content user data of the data set. One or more versions of data set group level error-correcting information for each data set group are calculated. The data set groups on stored a tape storage media. After the data set groups are stored, an amount of storage available on one or more regions of the tape storage media associated with one or more tape edges is identified. An instruction is provided to store at least a partial amount of the calculated one or more versions of data set group level error-correcting information for the data set groups able to be stored in the amount of storage available on the one or more regions of the tape storage media associated with the one or more tape edges.
US10854232B2
The magnetic recording medium includes a magnetic layer which contains ferromagnetic hexagonal ferrite powder and a binder, in which the magnetic layer contains an abrasive and a fatty acid ester, Int (110)/Int (114) of a crystal structure of the hexagonal ferrite, determined by performing XRD analysis on the magnetic layer by using an In-Plane method, is equal to or higher than 0.5 and equal to or lower than 4.0, a squareness ratio of the magnetic recording medium in a vertical direction is equal to or higher than 0.65 and equal to or lower than 1.00, FWHMbefore and FWHMafter is greater than 0 nm and equal to or smaller than 7.0 nm, and a difference between spacings measured within a surface of the magnetic layer by an optical interference method before and after the heating in a vacuum is greater than 0 nm and equal to or smaller than 8.0 nm.
US10854227B2
The magnetic recording medium includes a non-magnetic support and a magnetic layer which contains ferromagnetic powder and a binder, in which the ferromagnetic powder is ferromagnetic hexagonal ferrite powder, the magnetic layer contains an abrasive, Int (110)/Int (114) of a crystal structure of the hexagonal ferrite, determined by performing X-ray diffraction analysis on the magnetic layer by using an In-Plane method, to a peak intensity of a diffraction peak of (114) plane of the crystal structure is equal to or higher than 0.5 and equal to or lower than 4.0, a squareness ratio of the magnetic recording medium in a vertical direction is equal to or higher than 0.65 and equal to or lower than 1.00, and a logarithmic decrement obtained by performing a pendulum viscoelasticity test on a surface of the magnetic layer is equal to or lower than 0.050.
US10854226B2
Provided are a magnetic tape including: a non-magnetic support; and a magnetic layer including ferromagnetic powder and a binding agent on the non-magnetic support, in which the magnetic layer has a timing-based servo pattern, a center line average surface roughness Ra measured regarding a surface of the magnetic layer is equal to or smaller than 1.8 nm, the ferromagnetic powder is ferromagnetic hexagonal ferrite powder, an intensity ratio of a peak intensity of a diffraction peak of a (110) plane with respect to a peak intensity of a diffraction peak of a (114) plane of a hexagonal ferrite crystal structure obtained by an X-ray diffraction analysis of the magnetic layer by using an In-Plane method is 0.5 to 4.0, and a vertical direction squareness ratio of the magnetic tape is 0.65 to 1.00, and a magnetic tape device including this magnetic tape.
US10854220B2
A pitch detection method. Such a pitch detection method may use a Teager Energy Operator (TEO) with a Pseudo Weigner Ville Transformation (PWVT) to recover speech from noise and to recover low-frequency information of the speech signal in its detection of a pitch value. Also, the pitch detection method may use the combinatory PWVT and the respective state machine for decision making.
US10854211B2
An apparatus for encoding a multi-channel signal including at least two channels includes a time-spectral converter for converting sequences of blocks of sampling values of the at least two channels into a frequency domain representation having sequences of blocks of spectral values for the at least two channels; a multi-channel processor for applying a joint multi-channel processing to the sequences of blocks of spectral values to obtain at least one result sequence of blocks of spectral values including information related to the at least two channels; a spectral-time converter for converting the result sequence of blocks of spectral values into a time domain representation including an output sequence of blocks of sampling values; and a core encoder for encoding the output sequence of blocks of sampling values to obtain an encoded multi-channel signal.
US10854204B2
Some aspects of the invention may include a computer-implemented method for enrolling voice prints generated from audio streams, in a database. The method may include receiving an audio stream of a communication session and creating a preliminary association between the audio stream and an identity of a customer that has engaged in the communication session based on identification information. The method may further include determining a confidence level of the preliminary association based on authentication information related to the customer and if the confidence level is higher than a threshold, sending a request to compare the audio stream to a database of voice prints of known fraudsters. If the audio stream does not match any known fraudsters, sending a request to generate from the audio stream a current voice print associated with the customer and enrolling the voice print in a customer voice print database.
US10854203B2
A personal information assistant computing system may include a user computing device having a processor and a non-transitory memory device storing instructions. The personal information assistant may receive a user accessible input as a natural language communication from the user, which may be analyzed by a personal information assistant to determine a task to be performed by the virtual information assistant. The personal information assistant may be personalized to the user using encrypted user information. The personal information assistant communicates with a remote computing system in performance of a computer-assisted task, wherein the first personal information assistant interacts as a proxy for the user in response to at least one response received from the remote computing system. The personal information assistant may communicate the results of the task to the user via a user information screen and/or an audio device.
US10854184B2
A friction damped insert for highly stressed engineering components is disclosed. The disclosed inventive concept provides a method and system for increasing the damping capacity of an engineering system by adding a non-flat solid, highly damped insert to a system component that contributes most to the system's dynamic response. The insert can either be embedded into a system component during casting or be fastened to the system component outer surface. The insert is made of the single layer of flexible material by forming it into a rigid elongated body. The layer of material can be turned over on itself without folding to create a cylinder or can be folded over a number of times to create a prismatic bar. The layer of material may be shaped into a corrugated panel. The layer of flexible material may have a number of relatively small openings or perforations with a uniform spatial distribution.
US10854180B2
An automated music composition and generation system and process for producing one or more pieces of digital music, by providing a set of musical energy (ME) quality control parameters to an automated music composition and generation engine, applying certain of the selected musical energy quality control parameters as markers to specific spots along the timeline of a selected media object or event marker by the system user during a scoring process, and providing the selected set of musical energy quality control parameters to drive the automated music composition and generation engine to automatically compose and generate one or more pieces of digital music with control over the specified qualities of musical energy embodied in and expressed by the piece of digital music to composed and generated by the automated music composition and generation engine.
US10854175B2
A computing device monitors support element strain to enable deployment of positionally-related components in conjunction with one another while the real-time positional relationship between these positionally-related components fluctuates during operation. An exemplary computing device includes a first component and a second component that are both mounted to a support element. The computing device may be subjected to mechanical loading during operation which may induce strain into the support element thereby affecting the nominal positioning between the positionally-related components. The computing device includes a displacement sensor to generate displacement data that is indicative of a real-time positional relationship between the components. This real-time positional relationship may be compensated while implementing desired functionality. In this way, the computing device can be subjected to the stresses and strains that result from many typical use cases while the positional relationship between the sensor components is actively monitored and compensated for to implement desired functionality.
US10854156B2
A display device includes a plurality of pixels arranged in a matrix. Overlapping areas between gate electrodes and drain electrodes of switching elements connected to a plurality of selected pixel electrodes are individually set to equalize or substantially equalize retention voltages Vd(+) (Vd(−)) of the selected pixel electrodes when a specific voltage of a first polarity is applied to the selected pixel electrodes. The source application section is controlled to apply to the source lines source signals Vsc each of which is corrected by superposing a correction voltage preset for each source line on the source signal Vs(−) (Vs(+)) in application of a voltage of a second polarity to the selected pixel electrodes.
US10854155B2
A display apparatus includes a display panel, a timing controller, a data driver, and a gate driver. The timing controller receives image data at a number of frames per second of a first level and generates a gate control signal and a data control signal. The timing controller includes an image converter that operates in film mode or normal mode when the input image data are moving image data, and that outputs film image data at a number of frames per second of second level lower than the first level during the film mode. The data driver applies a data voltage corresponding to the film image data to the display panel based on the data control signal. The gate driver applies a gate voltage to the display panel based on the gate control signal. The display panel operates at a frequency of the second level during the film mode.
US10854148B2
The present disclosure proposes a method and a system of controlling backlight driving. The method includes receiving an initial-pulse-width modulating signal and outputting a corresponding pulse-width modulating signal according to the initial-pulse-width modulating signal. The pulse-width modulating signal is used to control a corresponding LED string to illuminate. A cycle of each of the pulse-width modulating signals is the same with a predetermined phase difference.
US10854144B2
A display device includes a display panel, a dimming controller, and a panel driver. The display panel includes a plurality of pixels. The dimming controller generates at least one temporary voltage set by performing a first interpolating operation using a (j)th band voltage set and a (j+1)th band voltage set among first through (i)th band voltage sets corresponding to first through (i)th dimming bands, respectively, and generates a grayscale gamma voltage set corresponding to target luminance by performing a second interpolating operation using the temporary voltage set and the (j)th band voltage set. The panel driver drives the display panel by converting image data into a data signal based on the grayscale gamma voltage set and by providing the data signal to the pixels.
US10854142B2
A display device includes a pixel circuit, a driving circuit configured to drive a data line coupled to the pixel circuit, and a first capacitance element provided between the data line and the driving circuit, wherein the driving circuit includes a second capacitance element, and a first switching circuit configured to alternately repeat charging and discharging of the second capacitance element, and is configured to control the charging and the discharging based on a gradation specified by the pixel circuit, and output a voltage signal corresponding to the gradation.
US10854134B2
Disclosed is a source signal driving apparatus capable of implementing channels at high integration density. The source signal driving apparatus is configured to sequentially output source signals by sequentially delaying enable time points of enable signals provided to channel circuits.
US10854126B1
A display device comprises a plurality of pixel unit sets and a plurality of common electrode (VCOM) signal generation circuits. Each of the pixel unit sets comprises a first portion pixel unit and a second portion pixel unit. Each of the first portion pixel unit and each of the second portion pixel unit comprise a plurality rows of pixel units. Each row of the pixel units comprises a plurality of pixel units. The VCOM signal generation circuits are respectively coupled to one of the pixel unit sets. The VCOM signal generation circuits are divided into a plurality of groups of number m. The VCOM signal generation circuits in each of the groups generate a first VCOM signal and a second VCOM signal to the coupled pixel unit set according to a first clock signal, a second clock signal and one of a plurality control signal sets of number m.
US10854114B2
By introducing inequality to the information dispersal/sharing storage method, a ciphertext management method or the like is provided to support novel ciphertext data management. After the ciphertext and key data are each divided, pairs of the divided ciphertext and key data are generated. Specifically, they are one-to-one paired as with conventional techniques. Furthermore, additional one-to-many pairs are generated. The generated one-to-one pairs provide equality as with conventional techniques. When the number of the one-to-one pairs of the divided ciphertext and key data that can be used is equal to or greater than a threshold number, both the ciphertext data and the key data can be reconstructed, and accordingly, the secret data can be decoded. In contrast, even when the one-to-many pairs that can be used is equal to or greater than a threshold number, the ciphertext data and/or the key data cannot be reconstructed. This provides inequality.
US10854110B2
Aspects of the present disclosure relate to systems and methods that aid users with hearing and/or speech impediments to have a conversation with a remote phone number without human assistance. In one aspect, an application residing on a user's device, such as a smartphone, tablet computer, laptop, etc., may be used to initiate a phone call to a recipient. Upon initiating the phone call locally, a service residing on the server may receive a request to initiate a connection to the recipient. Once the recipient answers, the user may converse with the recipient by providing text input to their local app. The text input may be transmitted to the service. The service may use a text to speech converter to translate the received text to speech that can be delivered to the recipient.
US10854107B2
A pair of training scissors structurally configured to help a child learn proper finger positions for use of scissors. The handles include solid bowl apertures to positioned so that the tips of the fingers are desirably positioned so that the tips of the fingers are utilized to operate the scissors. The scissors also include an illumination feature that encourages a child to practice opening and closing the scissors as they are motivated by the light. This repetition serves to reinforce the proper finger positions, and the repetitions also help develop muscle strength.
US10854106B2
A computer-based language learning system uses targeted repetition to familiarize a student with words and language governing rules. Targeted repetition presents practice-sentences made up of specific words and rules the language learning system has targeted for practice, with the intervals between encounters of targeted words and rules varying based on prior incorrect, correct and partially correct responses to the rule-items. Targeted reinforcement determines manner of response to practice-sentences. Learning records for each word and rule track information used in calculating an up-to-the-moment ‘need to practice’ rating for the rule-item. Learning records also track each prior response to the item, allowing the language learning system to determine the aspects of the word or rule-item of which a student lacks mastery. The language learning system provides targeted reinforcement by drilling the student on the particular aspect of the rule needing practice, along with the practice-sentence incorporating it.
US10854087B2
The present disclosure relates to an assistance system for a first vehicle, comprising a detection unit for detecting accident- and/or breakdown-related data from at least one device in a vehicle, a position determining unit for determining the current position of the first vehicle, an evaluation unit for evaluating data detected by the detection unit and the position determining unit, and a communication unit for issuing data using radio signals—automatically or following the triggering of an actuating unit in the vehicle—concerning an area around the current position of the first vehicle to be avoided by other road users using the communication unit if the evaluation unit has determined—based on the evaluation of the data collected—that the first vehicle has suffered an accident or that the first vehicle has experienced a breakdown.
US10854075B2
The network system triggers registration of the start of a transport journey in response to a communication of a transport user device and a transport provider device with each other, performs a continuous coordinated proximity monitoring to verify the identity of a transport user and a transport provider vehicle, and triggers registration of the end of the transport journey through communication of the transport user device and the transport provider device with each other.
US10854070B2
A load control system may include multiple control devices that may send load control messages to load control devices for controlling an amount of power provided electrical loads. To prevent collision of the load control messages, the load control messages may be transmitted using different wireless communication channels. Each wireless communication channel may be assigned to a load control group that may include control devices and load control devices capable of communicating with one another on the assigned channel. A control device may send load control messages to a load control device within a transmission frame allocated for transmitting load control messages. The transmission frame may include equal sub-frames and load control messages may be sent at a random time within each sub-frame. Control devices may detect a status event within a sampling interval to offset transmissions from multiple control devices based on detection of the same event.
US10854069B2
Embodiments of a central security monitoring device for reducing incidences of false alarms in a security system is disclosed. In one embodiment, a method is described, comprising receiving an alarm signal from an occupancy sensor via a receiver, receiving a second alarm signal from a barrier alarm device after receiving the alarm signal, determining, by a processor, an elapsed time from when the alarm signal from the occupancy sensor was received to when the second alarm signal from the barrier alarm device was received, transmitting, by the processor via a network interface, a message to a personal communication device indicating that a false alarm has occurred when the elapsed time is less than the predetermined time.
US10854061B2
An adaptive method and system for monitoring a shipping container for an environmental anomaly uses sensor-based ID nodes within the container and a command node. Sensors on each ID node generate sensor data about an environmental condition proximate the ID node as disposed within the container. Each ID node periodically broadcasts the sensor data. The command node monitors a first group of sensor data from the ID nodes over a first time period to detect an initial environmental threshold condition related to the container, then monitors a subsequent group of sensor data over a second time period under a modified monitoring parameter to detect a secondary environmental threshold condition related to the container as the anomaly. In response to detecting the secondary condition, the command node generates an alert notification and transmits the alert notification to an external transceiver to initiate a mediation response related to the anomaly.
US10854057B2
A similarity computation unit (130) derives a first probability P indicating that a first moving body appearing in the first video is the same as a second moving body appearing in the second video on the basis of similarity of feature value of the moving bodies. A non-appearance probability computation unit (140) derives a second probability Q indicating that the first moving body is not the same as the second moving body on the basis of an elapsed time after the first moving body exits from the first video. A person determination unit (150) determines whether the first moving body is the same as the second moving body by comparing the probability P and Q.
US10854046B2
Disclosed herein are systems and methods for facilitating cash payment for online gaming including receiving player information at a service provider system through an input element of a player input screen presented on a player system. Embodiments include presenting information regarding a point-of-service that is equipped to accept cash payments, generating a token that is optically readable for use by the point-of-service, determining if the point-of-service is located in a geographic region authorized to make payments to the game provider; and notifying the point-of-service to reject any payments from the player system if the point-of-service is not located in a geographic region authorized to make the payments from the player system to the game provider.
US10854045B2
Methods and systems for electronic interaction comprising a display for presenting a grid of identifying objects, an input for receiving a player selection of an identifying object, a random generator for randomly selecting a winning identifying object, and a point tally system for awarding points to the player according to the rules comprising a first point value if the player selected identifying object exactly matches the winning identifying object, a second point value if the player selected identifying object is in a geometric relationship with the winning identifying object, and a third, negative, point value if the player is not awarded the first point value or the second point value.
US10854044B2
An electronic gaming machine (EGM) may present first visual effects on a display system, including game play items, corresponding to one or more instances of a base game and determining instances of game play items that correspond to feature credits towards an automatic award of a feature comprising one or more bonus games. The EGM may present second visual effects corresponding to an accumulation of feature credits towards the automatic award of the feature, receive an indication of a player's initiation of an attempt to trigger an award of the feature, at a time during which less than a number of feature credits necessary for an automatic award of the feature has been accumulated, determine whether an award of the feature will be triggered and control the display system to present third visual effects corresponding to whether an award of the feature has been triggered.
US10854030B2
A method, an apparatus and a system relate to processing a transport container for objects of value, particularly value documents, such as for example banknotes. The method comprises the steps of feeding the transport container to an apparatus for processing the transport container, opening the transport container in the apparatus, emptying the objects of value from the transport container, and checking the transport container for a residual quantity. For the check, electromagnetic radiation is applied to the transport container, wherein a transmission image of the transport container is produced by means of the electromagnetic radiation. The residual quantity in the transport container is deduced by means of the analysis of the transmission image.
US10854018B2
A method for calculating a fare for a transport service is provided. One or more processors receive a plurality of location data points from a computing device associated with a vehicle providing the transport service. The plurality of location data points correspond to a route of travel during performance of the transport service. A determination is made, based on a set of location data points of the plurality of location data points, that the vehicle has potentially driven along a roadway in which a toll is to be assessed as part of the fare. The roadway in which the toll is to be assessed is identified. The amount for the toll is determined for the identified roadway.
US10854013B2
Described herein are systems and methods for presenting building information. In overview, the technologies described herein provide relationships between Building Information Modeling (BIM) data (which includes building schematics defined in terms of standardized three dimensional models) and Building Management System (BMS) data (which includes data indicative of the operation of building components such as HVAC components and the like). Some embodiments use relationships between these forms of data thereby to assist technicians in identifying the physical location of particular pieces of equipment, for example in the context of performing inspections and/or maintenance. In some cases this includes the provision of 2D and/or 3D maps to portable devices, these maps including the location of equipment defined both in BIM and BMS data. In some cases, augmented reality technology is applied thereby to provide richer access to positional information.
US10854010B2
Provided is a method, performed by a device, of processing an image, the method including tracking a movement of a user wearing the device and generating movement information of the user, the movement information being about a movement occurring between a previous time when a first image was rendered and a current time when a second image is rendered; selecting at least one pixel from among a plurality of pixels comprised in the first image, based on the generated movement information and a location of a target pixel comprised in the second image; and changing a value of the target pixel by blending a value of the selected at least one pixel with the value of the target pixel according to a preset weight.
US10854004B2
In one embodiment, a method includes receiving first information from a sensor associated with a first computing device, wherein the first information comprises information associated with first images captured at the first sensor; receiving second information from a second computing device, wherein the second information comprises information associated with second images captured at a sensor associated with the second computing device; identifying first points within the first images; identifying second points within the second images; and relocalizing the first and second computing devices within a shared augmented-reality environment by defining coordinate spaces based on the images and combining the coordinate spaces based on identified shared points.
US10853997B2
In some examples, octree serialization can include non-transitory machine-readable medium storing instructions, the instructions executable by a processing resource to evaluate two or more nodes sequentially in an octree structure until a leaf node is reached, wherein the two or more nodes include at least one non-leaf node, and generate a serialized octree document based on a respective node identifier in a header associated with each node of the two or more nodes.
US10853994B1
The disclosure is directed to methods and processes of rendering a complex scene using a combination of raytracing and rasterization. The methods and processes can be implemented in a video driver or software library. A developer of an application can provide information to an application programming interface (API) call as if a conventional raytrace API is being called. The method and processes can analyze the scene using a variety of parameters to determine a grouping of objects within the scene. The rasterization algorithm can use as input primitive cluster data retrieved from raytracing acceleration structures. Each group of objects can be rendered using its own balance of raytracing and rasterization to improve rendering performance while maintaining a visual quality target level.
US10853992B1
Systems and methods for displaying a three-dimensional (3D) model of a real estate property are disclosed. An exemplary system may include a display device, a memory storing computer-readable instructions and at least one processor. The processor may execute the computer-readable instructions to perform operations. The operations may include determining a field of view (FOV) of a virtual observer of the 3D model based on a view point of the virtual observer in the 3D model. The FOV may cover a subset of the 3D model. The operations may also include determining, based on a floor plan corresponding to the 3D model, feature information of a functional space that at least partially fall within the FOV or connect to the subset of the 3D model covered by the FOV. The operations may further include controlling the display device to display the subset of the 3D model along with the feature information.
US10853989B2
Embodiments described herein provide an apparatus comprising a processor to maintain a plurality of first-in first-out (FIFO) queue structures in a computer readable memory, each of the plurality of FIFO queue structures corresponding to a coarse selection dispatch rate, receive a request message to dispatch coarse compute shader work, the request message comprising a requested coarse selection dispatch rate and a thread identifier, and store the request message in a FIFO queue structure having a coarse selection dispatch rate corresponding to the requested coarse selection dispatch rate associated with the request message. Other embodiments may be described and claimed.
US10853987B2
A system and method for generating cartoon images from photos are described. The method includes receiving an image of a user, determining a template for a cartoon avatar, determining an attribute needed for the template, processing the image with a classifier trained for classifying the attribute included in the image, determining a label generated by the classifier for the attribute, determining a cartoon asset for the attribute based on the label, and rendering the cartoon avatar personifying the user using the cartoon asset.
US10853981B2
Systems and methods are provided for providing a timeline representing a culture media protocol for a culture medium. Providing a timeline representing a culture media protocol can include receiving the culture media protocol for the culture media generating the timeline on a user interface based on the culture media protocol, monitoring time on the timeline, receiving one or more culture media images related to the culture media protocol, associating each of the one or more culture media images with a position on the timeline that correlates to a time at which the culture media image was captured, and generating a selectable marker for each culture media image associated with the timeline, the selectable marker being aligned with the position on the timeline that correlates to the time at which the culture media image was captured.
US10853974B2
A decoding device, an encoding device and a method for point cloud decoding is disclosed. The method includes receiving a compressed bitstream. The method also includes decoding the compressed bitstream into 2-D frames that represent a 3-D point cloud. Each of the 2-D frames including a set of patches, and each patch includes a cluster of points of the 3-D point cloud. The cluster of points corresponds to an attribute associated with the 3-D point cloud. One patch of the set of patches, the set of patches, and the 2-D frames correspond to respective access levels representing the 3-D point cloud. The method also includes identifying a first and a second flag. In response to identifying the first and the second flag, the method includes reading the metadata from the bitstream. The method further includes generating, based on metadata and using the sets of 2-D frames, the 3-D point cloud.
US10853969B2
A method for supporting image processing for a movable object includes acquiring one or more images captured by an imaging device borne by the movable object. The imaging device is at least partially blocked by an obstructive object attached to the movable object. The method further includes applying a template to the one or more images to obtain one or more projected locations of the obstructive object within the one or more images and detecting at least portion of the obstructive object at the one or more projected locations within the one or more images.
US10853968B2
The geometric pose of a patch of watermark data is estimated based on the position of a similar, but non-identical, patch of information within a data structure. The information in the data structure corresponds to a tiled array of calibration patterns that is sampled along at least three non-parallel paths. In a particular embodiment, the calibration patterns are sampled so that edges are globally-curved, yet locally-flat. Use of such information in the data structure enables enhanced pose estimation, e.g., speeding up operation, enabling pose estimation from smaller patches of watermark signals, and/or enabling pose estimation from weaker watermark signals. A great variety of other features and arrangements are also detailed.
US10853964B2
An image recognition system includes a first computer for detecting a recognition target from image data, and a second computer for identifying the recognition target detected by the first computer. The first computer and the second computer are disposed at positions physically separated from each other. When the first computer sends image data to the second computer, the second computer sends to the first computer a detection parameter group used for detection via a communication path. The detection parameter group is included in a recognition parameter group that is dynamically changed and used for image recognition processing of the image data.
US10853961B1
Techniques are disclosed for generating a low-dimensional representation of an image. An image driver receives an image captured by a camera. The image includes features based on pixel values in the image, and each feature describes the image in one or more image regions. The image driver generates, for each of the plurality of features, a feature vector that includes values for that feature corresponding to at least one of the image regions. Each value indicates a degree that the feature is present in the image region. The image driver generates a sample vector from each of the feature vectors. The sample vector includes each of the values included in the generated feature vectors.
US10853953B2
A method of operating a video camera system comprises recording video frames of a scene that includes a zone defined as an area within a field-of-view of the video capture element; performing a first analysis of recorded video frames showing the zone, determining, based on the first analysis, a first difference of composition thereof; performing a second analysis of an area outside of the zone; determining, based on the second analysis, a second difference of composition thereof; characterizing one or more properties corresponding to the second difference in composition; determining whether the one or more properties are associated with the first difference in composition within the zone and if so, characterizing the first difference in composition within the zone based on the one more properties and performing an action based on the characterization of the first difference in composition within the zone based on the one or more properties.