This invention discloses a method for automatically generating an integrated circuit layout, the method comprises determining a first cell height, creating a plurality of standard cells all having the first cell height, and generating the IC layout from the plurality of standard cells by placing and routing thereof. The method for generating the integrated circuit layout comprises the steps of marking a specific element by means of a markup layer so as to prepare a transition layout; and preparing a plurality of required layout variations through applying at least one logical operation on the transition layout so as to retrieve a database so as to generate a final integrated circuit layout, wherein the layout change variations comprises the conditions of widening the transistor channel length of a specific element and setting a virtual structure in the final integrated circuit layout. The invention improves the utilization of layout area of the integrated circuit. The element is able to be easily replaced because the arrangement of the element is in the grid. The circuits between elements are easily connected owing to contact alignment between elements.