The invention discloses a lower hardware mapping method and device of an integrated circuit. The method comprises the following steps: a program analysis step: reading an analysis program and matching to obtain a mapped execution object and parameter object; a data control flow diagram generation step: mapping the execution object and parameter object to corresponding nodes in the data control flow diagram; an operator time-space diagram generation step: taking out a corresponding operator unit from an operator unit library to expand the data control flow diagram into an operator time-space diagram; a time sequence constraint step: performing time sequence constraint on each layer of the operator time-space diagram according to the total time sequence constraint; and a time-space diagram compression step: performing spatial cluster compression on the time-space diagram according to a time label. The invention also discloses a time-space diagram compression method and device, wherein the method comprises a step of spatially merging and compressing operators with the same operation attribute and/or storage attribute by introducing a control operator. By using the method and device, the design speed of the integrated circuit is increased.