The present invention discloses a circuit and a method used for testing an integrated circuit (IC). A circuit block comprises a selector circuit which is connected to receiving an enable signal and two clock signals; wherein, based on the enable signal, one of the two clock signals is selected to be used as an input of the selector circuit; a storage element is connected to receive the enable signal and an output of the selector circuit for being used as a clock input signal; a logic gate is connected to receive an output of the storage element and the enable signal; another selector circuit is connected to receive an output from the logic gate and the enable signal; and the selector circuit selects the output of the logic gate or the enable signal to be used as a scan enable signal of a scan chain on the IC.