The invention discloses an electrically-erasable and programmable read-only memory which at least comprises a semiconductor substrate, a first bit line, a second bit line, a first floating gate, a second floating gate, a first control gate, a second control gate and a word line. An N-type high-doping source electrode region, a drain electrode region and a channel region are arranged on the semiconductor substrate, the source electrode region and the drain electrode region are arranged at an interval, and the channel region is located between the source electrode region and the drain electrode region. The first bit line and the second bit line are connected to the source electrode region and the drain electrode region respectively. The first floating gate is arranged above the channel region and the source electrode region. The second floating gate is arranged above the channel region and the drain electrode region. The first floating gate and the second floating gate form a first storage bit unit and a second storage bit unit respectively. The first control gate is arranged above the first floating gate, and the second control gate is arranged above the second floating gate. The word line is located above the channel region and between the first floating gate and the second floating gate. By means of the electrically-erasable and programmable read-only memory, using of a large number of word line voltage-selected switches is avoided, and the area of a chip is reduced.