The invention specifically relates to resistive random access memory equalization and sensing. Providing for a two-terminal memory architecture that can mitigate sneak path current in conjunction with memory operations is described herein. By way of example, a voltage mimicking mechanism can be employed to dynamically drive un-selected bitlines of the memory architecture at a voltage observed by a selected bitline. According to these aspects, changes observed by the selected bitline can be applied to the un-selected bitlines as well. This can help reduce or avoid voltage differences between the selected bitline and the un-selected bitlines, thereby reducing or avoiding sneak path currents between respective bitlines of the memory architecture. Additionally, an input/output based configuration is provided to facilitate reduced sneak path current according to additional aspects of the subject disclosure.