In an active region (100a), p+ regions (3) are selectively provided in the front surface layer of an n- drift layer (2) on an n+ semiconductor substrate (1). On the surfaces of the n- drift layer (2) and the p+ regions (3), p base layers (4) are provided, and on the p base layers (4), a MOS structure is provided. Other portions of the active region (100a) are provided with a p+ region (33) in contact with a source electrode (10), said p+ region being on the p+ regions (3). In a withstand voltage structure region (100b), a JTE structure (13) configured of at least a p- region (21) is provided by being separated from the p+ regions (3) and the p base layers (4) such that the JTE structure surrounds the active region (100a). At a portion where the MOS structure is not formed, said portion being in the vicinity of the boundary between the active region (100a) and the withstand voltage structure region (100b), the p- region (21) is in contact with the p+ region (33). Consequently, a semiconductor device, which has stable high withstand voltage characteristics and low on-resistance can be provided.