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发明公开
CN105099466A 一种用于128位并行数据的CRC校验矩阵生成方法 有权

一种用于128位并行数据的CRC校验矩阵生成方法
摘要：
本发明提供一种用于128位并行数据的CRC校验矩阵生成方法，减少了级联结构带来的链路延迟，实现高速串行通信中接收或发送数据的实时校验，用于128位并行数据的CRC校验矩阵的生成方法。该方法提供了直接对128并行数据进行CRC编解码的校验矩阵，从而避免使用延时较大的级联结构，提高了128位并行数据的CRC编解码效率，实现高速串行通信中接收或发送数据的实时校验。基于该校验矩阵的CRC电路可以用于PCIe 3.0物理层中的128位并行数据的实时CRC校验，保证了数据的高效率传输。
摘要（英）：

The invention provides a CRC (Cyclic Redundancy Check) matrix generating method for 128bit parallel data, which reduces link delay caused by a cascade structure, realizes real-time check of data received or transmitted in high-speed serial communication and is used for generating a CRC matrix for 128bit parallel data. The method provides a check matrix for directly performing CRC coding and decoding on 128bit parallel data, so as to avoid using a cascade structure with high delay, improve the CRC coding and decoding efficiency of the 128bit parallel data and realize real-time check of data received or transmitted in high-speed serial communication. A CRC circuit based on the check matrix can be used for real-time CRC of 128bit parallel data in a PCIe3.0 physical layer, thus ensuring high-efficiency transmission of data.

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