The present invention discloses a chip design stage reliability evaluation method and device. The method comprises dividing function modules according to determined chip functions and carrying out netlist design according to requirements of the function modules; carrying out pre-simulation on a netlist according to a BSIM device model, and carrying out layout drawing when a pre-simulation result meets the requirements of the function modules; extracting wired parasitic capacitors and resistors after the layout drawing is completed, and carrying out post-simulation on the extracted netlist according to the BSIM device model; carrying out simulation again on a pre-established burn-in BSIM device model when a post-simulation result meets the requirements of the function modules; and carrying out platemaking chip flowing when a third simulation result meets the requirements of the function modules. With adoption of the method and the device, in comparison with conventional development processes, a product development cycle can be shortened, times of modifying photoetching plates can be reduced, and the development cost is thus lowered.