The invention provides a burr-free switching circuit for supporting a multi-way clock. The burr-free switching circuit comprises a register, an AND gate, a first selector, a register group, a decoding circuit, a multi-clock interlock circuit and a clock selector; the decoding circuit realizes decoding of a one-hot encoding mode on a clock selection signal, and a log2N bit clock selection signal is translated into a decoding result of N bit one-hot encoding, so that the uniqueness and excludability of an effective clock enable signal can be guaranteed; meanwhile, the multi-clock interlock circuit processes the decoding result according to the currently outputted clock enable; if the currently outputted clock enable is not equal to the decoding result, then all clock enables are firstly closed, and then the decoding result is used as a new clock enable signal to open corresponding clocks, so that burr-free switching of a clock signal can be realized. The burr-free switching circuit for supporting the multi-way clock provided by the invention can realize burr-free switching of N paths of input clocks, support random switching orders, and provide greater flexibility for a work pattern of the whole circuit.