The invention relates to a hierarchical information processing method and circuit based on controller pipeline architecture. The hierarchical information processing method comprises the following steps: 1) a main processing core receives an input signal, and sends a configuration parameter to a lower-level configurable pipeline signal processing core according to the data processing requirement of the input signal; 2) the configurable pipeline signal processing core receives the configuration parameter, and feeds back the state information of the built-in state register of the configurable pipeline signal processing core to the main processing core, and 3) is executed if the state information of at least one configurable pipeline signal processing core is under an idle state; 3) the main processing core preferentially selects the configurable pipeline signal processing core of configuration matched with the data processing requirement of the input signal; and 4) the configurable pipeline signal processing core updates the own state register after the corresponding operation is finished, and simultaneously sends interruption to the main processing core to finish a data processing operation. The hierarchical information processing method has the characteristics of expandability, flexibility and variability.