The invention discloses a bit cycle method for improving the dynamic performance of a hybrid resistance and capacitance type analog to digital converter. The applied technical field is a high-precision analog to digital converter in the field of microelectronics and solid state electronics. The bit cycle method provided by the invention is applicable to successive approximation analog to digital converter of any structure, the core idea is to split a most significant bit (MSB) capacitance and secondary most significant bit (MSB-capacitance), a capacitance array is divided into four groups, and the capacitance order is changed in each bit cycle to a dynamic averaging effect of capacitance errors is realized. The bit cycle method is characterized in that no correction algorithm needs to be introduced, no correction DAC needs to be introduced, the sampling rate of the analog to digital converter is not sacrificed, and the normal operation of the analog to digital converter is not interrupted. The bit cycle method provided by the invention can be used for carrying out dynamic averaging on the capacitance errors, therefore compared with the traditional correction method that depends on the correction DAC and the correction algorithm to improve the linearity, the structure is simpler, the occupied chip area is smaller, and a on-chip effect is realize more easily.