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发明公开
CN107845617A 一种芯片烧结品、子单元、IGBT封装模块及制备方法 有权

一种芯片烧结品、子单元、IGBT封装模块及制备方法
摘要：
本发明公开了一种芯片烧结品、子单元、IGBT封装模块及制备方法。该芯片烧结品包括第一钼片和第二钼片以及设置于两者间的芯片，第一钼片和第二钼片中至少一个为预制钼片，预制钼片为表面设置预制纳米银膜的钼片，且芯片中至少一面与预制纳米银膜相接触，通过采用预制纳米银膜能有效提高后续加压烧结过程中纳米银颗粒的分布均匀性，避免“咖啡环效应”，降低了热阻。同时保证由其烧结得到的烧结层中分布均匀的纳米级孔洞，通过这些纳米级孔洞能有效降低芯片和钼片间产生的应力，提高芯片烧结品的剪切强度。采用该芯片烧结品的单元和IGBT封装模块具有低的热阻、高的剪切强度，由预制纳米银膜烧结得到的烧结层致密性高，且分布纳米级孔洞。
摘要（英）：

The invention discloses a chip sintered product, a sub unit, an IGBT packaging module and a preparation method. The chip sintered product comprises a first molybdenum sheet, a second molybdenum sheetand a chip placed between the first and second molybdenum sheets; at least one of the first and second molybdenum sheets is a prefabricated molybdenum sheet; the prefabricated molybdenum sheet is a molybdenum sheet with a prefabricated nanometer silver film on the surface; in addition, at least one surface of the chip is in contact with the prefabricated nanometer silver film; by adoption of the prefabricated nanometer silver film, distribution uniformity of nanometer silver particles in the subsequent pressuring and sintering process can be improved effectively, a "coffee ring effect" can beavoided, and thermal resistance can be lowered; meanwhile, it is ensured that nano-scale holes are uniformly distributed in a sintering layer obtained by sintering, and by virtue of the nano-scale holes, stress generated between the chip and the molybdenum sheet can be lowered effectively, and the shearing strength of the chip sintered product is improved; and by adoption of the chip sintered product and the IGB packaging module with low thermal resistance and high shearing strength, the sintering layer obtained by sintering the prefabricated nanometer silver film has high compactness, and thenano-scale holes are distributed.

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