发明公开
- 专利标题： Gate turn-off thyristor
- 专利标题（中）： 通过控制电极断晶闸管。
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申请号： EP79301874.8申请日： 1979-09-12
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公开(公告)号： EP0009367A1公开(公告)日： 1980-04-02
- 发明人: Nagano, Takahiro , Sanpei, Isamu , Sakurada, Shuroku , Nakagawa, Masaru
- 申请人： Hitachi, Ltd.
- 申请人地址： 5-1, Marunouchi 1-chome Chiyoda-ku, Tokyo 100 JP
- 专利权人： Hitachi, Ltd.
- 当前专利权人： Hitachi, Ltd.
- 当前专利权人地址： 5-1, Marunouchi 1-chome Chiyoda-ku, Tokyo 100 JP
- 代理机构： Paget, Hugh Charles Edward
- 优先权： JP112257/78 19780914
- 主分类号： H01L29/08
- IPC分类号： H01L29/08 ; H01L29/743
摘要：
A gate turn-off thyristor of a short-circuited emitter configuration comprises a semiconductor substrate (1) of a P E -N B -P B -N E four-layer structure, wherein a P E -layer (2) is short-circuited through a N B -layer (3 and 4) and an anode (8). The N B -layer includes heavily doped regions (3) with which the anode is in ohmic contact with low resistance. The P E -layer (2) is at least partly at the area corresponding to the projection of the N E -layer (6) onto the surface contacted by the anode (8). The thickness of the heavily doped regions (3) is greater than of the P E -layer (2). This structure achieves satisfactory gate turn-off characteristics, although the semiconductor substrate is not doped with a life time killer impurity.
公开/授权文献
- EP0009367B1 Gate turn-off thyristor 公开/授权日：1985-02-06
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