发明公开
- 专利标题： LOGIC GATE STRUCTURE USING SPACE CHARGE LIMITED TRANSISTORS
- 专利标题（中）： 逻辑门结构使用空间充电有限公司的晶体管
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申请号： EP82400444申请日： 1982-03-12
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公开(公告)号： EP0061387A3公开(公告)日： 1983-08-31
- 发明人: VORA, MADHUKAR B.
- 申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
- 专利权人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
- 当前专利权人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION
- 优先权： US24444081 1981-03-16
- 主分类号： H01L29/80
- IPC分类号： H01L29/80 ; H01L21/331 ; H01L21/337 ; H01L21/8222 ; H01L27/07 ; H01L27/082 ; H01L29/73 ; H01L29/808 ; H03K19/091 ; H01L27/04 ; H01L21/82
摘要：
An intregrated circuit structure is disclosed in which a pair of complementary lateral space charge limited transis tors are formed together with at least one Schottky diode to create a logic gate. The structure includes a semiconductor substrate, a first and a second region of N conductivity type spaced apart in the substrate, a third and a fourth region of P conductivity type, the third region separating the first region from the second region, and the second region separating the third region from the fourth region. The first region has a graduated impurity concentration which is less than 10¹⁸ atoms per cubic centimeter at the surface and at least 10¹⁸ atoms per cubic centimeter at a selected depth below the surface of the substrate.
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