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247 条记录 (耗时 0.026 秒)

    Multiple port pipelined processor
    1.
    发明公开
    Multiple port pipelined processor 失效
    多端口管道处理器

    公开(公告)号：EP0136218A3

    公开(公告)日：1988-04-20

    申请号：EP84401713

    申请日：1984-08-24

    申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

    发明人： Lyon, Richard F.

    IPC分类号： G06F15/06

    CPC分类号： G06F15/8007

    摘要： A horizontal computation device includes a multi-ported random access memory in combination with independent pipelined memoryless function modules. The device is operative to implement a class of algorithms involving a high ratio of arithmetic computation to control complexity and good locality of data reference. The invention meets the criterion of a horizontal computation machine without undue complexity, that is, the invention provides a structure wherein a delay element capable of arbitrary delay can be allocated between every resource or function output and every resource or function input. The structure is a parallel input, parallel output random access memory having a plurality of dedicated serial buffered input ports and dedicated serial buffered output ports. The buffered ports are operative to provide transient storage in independent pipelines and parallel input and output to addressed locations of the random access memory. The invention also encompasses a program compilation technique and a multiple address bus primitive cell for a dynamic random access memory.

    摘要翻译： 水平计算装置包括与独立流水线无记忆功能模块组合的多端口随机存取存储器。 该装置用于实现涉及高比例的算术计算的算法以控制数据参考的复杂性和良好的局部性。 本发明符合水平计算机的标准，不需要过多的复杂性，即本发明提供一种结构，其中可以在每个资源或功能输出与每个资源或功能输入之间分配能够任意延迟的延迟元件。 该结构是具有多个专用串行缓冲输入端口和专用串行缓冲输出端口的并行输入并行输出随机存取存储器。 缓冲端口可操作以在独立管线中提供瞬态存储，并且将并行输入和输出提供给随机存取存储器的寻址位置。 本发明还包括用于动态随机存取存储器的程序编译技术和多地址总线原语单元。

    Method and apparatus for monitoring automated testing of electronic circuits
    2.
    发明授权
    Method and apparatus for monitoring automated testing of electronic circuits 失效
    用于监测电子电路自动测试的方法和装置

    公开(公告)号：EP0136206B1

    公开(公告)日：1988-03-30

    申请号：EP84401609.7

    申请日：1984-08-01

    申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

    发明人： Schinabeck, John

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31935 ,  G01R31/31713 ,  G01R31/3191 ,  G01R31/31922 ,  G01R31/31924 ,  G01R31/31926 ,  G01R31/31928 ,  G01R31/31937 ,  G11C7/22 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00247 ,  H03K2005/00254 ,  H03K2005/0026

    摘要： A timing subsystem 10 including several test period generators for supplying a variety of timing signals to a device under test. Major, minor, and free-run period generators each supply various timing signals to a multiplexer 18, which selectively connects the timing signals to timing generators 20. A central processing unit 28 supplies data to the period generators and timing generators to define their respective timing signals. Timing signals generated by the major period generator 12 define the overall testing rate. The minor period generator 14 generates multiple timing signals within the periods of the major clock signals to permit higher clock rates. Timing signals that are independent of the major clock periods are generated by the free-run period generator 16. An external synchronizer circuit 26 provides a feedback loop from the device under test 22 to the major period generator. A reference driver trigger delay circuit 27 provides means for calibrating the timing generators. Each of the three period generators includes two interconnected timing interval generators 30 and 40 that alternately generate overlapping timing signals. Each timing interval generator includes a stop-restart oscillator 32, a counter 34, and a delay-line vernier 36. Upon the receipt of a start signal, the oscillator stops and restarts to align its clock pulses to the start signal. The oscillator output clocks the counter, which supplies a signal to the vernier when a preselected number is reached. The vernier delays the counter signal by a preselected delay and issus a signal that designates the end of the period.

    Self-aligned silicide base contact for bipolar transistor
    5.
    发明公开
    Self-aligned silicide base contact for bipolar transistor 失效
    用于双极晶体管的双极转移对准的硅酮基接触件的自对准硅酮基接触器

    公开(公告)号：EP0168324A3

    公开(公告)日：1988-01-07

    申请号：EP85401385

    申请日：1985-07-09

    申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

    发明人： Kapoor, Ashok K. ,  Hingarh, Hemraj K.

    IPC分类号： H01L21/28 ,  H01L29/60 ,  H01L29/72

    CPC分类号： H01L21/76897 ,  H01L21/76889 ,  H01L29/42304 ,  H01L29/66272

    摘要： A self-aligned silicide base contact structure for a bipolar transistor, and a process for fabricating the structure are disclosed. The structure has four key elements: a base region 36, a polycrystalline silicon emitter contact region 50, a spacer oxide 60 and 62, and a base contact 74 formed of metal silicide. The spacer oxide is an insulator that electrically isolates the side walls of the emitter contact region from the upper surface of the base region. The spacer oxide is a residual amount of oxide that is left on the side walls of the emitter contact region after anisotropic etching is used to remove most of a covering layer of oxide. The metal silicide base contact is created on an exposed upper surface of the base region, and is formed by first depositing a metal layer on the upper surface of the base region, and then heat treating. Where metal and silicon atoms are in contact, such as along the exposed upper surface of the base region, metal silicide forms.

    Multiple phase-splitter TTL output circuit with improved drive characteristics
    7.
    发明公开
    Multiple phase-splitter TTL output circuit with improved drive characteristics 失效
    具有改进驱动特性的多相分相器TTL输出电路

    公开(公告)号：EP0169782A3

    公开(公告)日：1987-06-03

    申请号：EP85401473

    申请日：1985-07-18

    申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

    发明人： Ferris, David A. ,  Caswell, Richard J.

    IPC分类号： H03K19/088 ,  H03K19/013

    CPC分类号： H03K19/088 ,  H03K19/0136

    摘要： A multiple phase-splitter TTL tristate output circuit having a feedback diode coupled between the signal output and the collector of a first phase-splitter transistor to accelerate sinking of current from the output to low potential during transition of binary signals at the output from high to low potential. An independent base drive is coupled to the base of the first phase-splitter transistor independent from any base drive coupled to the other phase-splitter transistor or transistors. Current hogging of the base drive current to the first phase-splitter transistor by the other phase-splitter transistors is thereby prevented. The first phase-splitter transistor which is coupled in the feedback circuit with the accelerating feedback diode to the base of the pulldown transistor element can therefore maintain the high current sinking mode through the pulldown transistor element with gain step-up proportional to β wnen the output is at the high voltage level.