与非易失性存储的n位的数字字的一个计数器中使用时，本发明涉及电可编程半导体存储器元件的劣化的问题。 此问题主要是由主存储（HS）为m的较高阶位+ 1到n和一个矩阵存储器（M）与含有作为主存储器（HS），电可编程存储器元件的存储器单元2 的存储器单元来解决。 所述存储器阵列的存储器元件（M）通过在时间上与在字移位寄存器（WSR），并且选择一个位的移位寄存器（BSR）的计数脉冲比特位，同时主存储器（HS）与一个二进制计数器（BZ）的用正性存储器单元的高次m位的纳米存储器单元 耦合。 此外，一个时钟顺序控制器（A）被提供，其通过第一输出的二进制计数器的（A1）（BZ）复位位移位寄存器（BSR）和所述字移位寄存器（WSR），并出现在其中一个读取周期的随后读取脉冲，其中，在主存储器中的信息 （HS）和在二进制计数器（BZ）的存储器阵列（M）中被写入，通过第二输出另外的（A2）中删除在由擦除脉冲到主存储（HS）的计数处理，并且所述存储矩阵（M），和2后< 米>计数删除，并且还经由第三输出（A3）之后，用写脉冲的每个计数通过另一擦除脉冲提供所述存储器阵列的字线，所述存储器阵列（M）。

The invention deals with the problem of degradation of electrically programmable semiconductor memory elements when used in a counter with non-volatile storage of an n-ary digital word. This problem is largely solved by a main storage (Hs) for the higher order bits of m + 1 to n and a matrix memory (M) with 2 ^m memory cells, which contain as the memory cells of the main memory (Hs) electrically programmable memory elements. The memory elements of the memory array (M) bit by bit in time with the pulses through a word shift register (WSR) and a bit shift register (BSR) is selected, while the nm memory cells of the main memory (Hs) with the more significant nm bits of a binary counter (Bz) with n-volatile memory cells are coupled. Further, a clocked sequence controller (A) is provided, which via a first output (A1) of the binary counter (Bz) resets the bit shift register (BSR) and said word shift register (WSR) and to which subsequently reading pulses of a reading cycle may arise where the information in main memory (Hs) and in the memory array (m) in the binary counter (Bz) to be written, further via a second output (A2) in the counting process by an erase pulse to the main memory (HS) and the memory array deletes (m), and after 2 ^m counts extinguished by a further erase pulse, the memory matrix (M) and which also has a third output (A3) supplies the word line of the memory matrix after each counting pulse with a write pulse.