发明公开
EP0073424A2 Central processing unit for executing instructions of variable length
失效
用于执行可变长度的指令的中央处理单元。
- 专利标题: Central processing unit for executing instructions of variable length
- 专利标题(中): 用于执行可变长度的指令的中央处理单元。
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申请号: EP82107598.3申请日: 1982-08-19
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公开(公告)号: EP0073424A2公开(公告)日: 1983-03-09
- 发明人: Fukunaga, Yasushi , Bandoh, Tadaaki , Hirasawa, Kotaro , Matsumoto, Hidekazu , Ide, Jushi , Katoh, Takeshi , Nakanishi, Hiroaki , Kawakami, Tetsuya , Hiraoka, Ryosei
- 申请人: Hitachi, Ltd. , Hitachi Engineering Co., Ltd.
- 申请人地址: 5-1, Marunouchi 1-chome Chiyoda-ku, Tokyo 100 JP
- 专利权人: Hitachi, Ltd.,Hitachi Engineering Co., Ltd.
- 当前专利权人: Hitachi, Ltd.,Hitachi Engineering Co., Ltd.
- 当前专利权人地址: 5-1, Marunouchi 1-chome Chiyoda-ku, Tokyo 100 JP
- 代理机构: Schulz, Rütger (DE)
- 优先权: JP132716/81 19810826; JP132717/81 19810826
- 主分类号: G06F9/34
- IPC分类号: G06F9/34 ; G06F9/30
摘要:
A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flag is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.
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