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12 条记录 (耗时 0.017 秒)

    A peripheral apparatus for image memories
    5.
    发明公开
    A peripheral apparatus for image memories 失效
    图像记忆的外围设备

    公开(公告)号：EP0176801A3

    公开(公告)日：1988-11-09

    申请号：EP85111248

    申请日：1985-09-05

    申请人： HITACHI, LTD.

    发明人： Kobayashi, Yoshiki ,  Takenaga, Hiroshi ,  Katoh, Takeshi

    IPC分类号： G09G01/16

    CPC分类号： G09G5/39

    摘要： A peripheral apparatus for image memories can communicate image data with a memory assembly composed on n blocks (60-63) of a standard-type DRAM, whether DRAM is of page mode or of nibble mode. The apparatus comprises a read data processing unit (82) sending the data of selected one among n pixels read from the DRAM blocks in parallel to an external image/graphics processor (2), a write data processing unit (84) modifying the image data taken thereinto and writing the modified data in the DRAM blocks, a feedback data (86) processing unit writing the image data now on displaying into the DRAM blocks after a desired processing again, a display data processing unit (88) sending the data read from the DRAM blocks to a monitor for display and to the external processor (2) for the feedback processing, and a control unit (80) furnishing control signals to those processing units in response to instructions from the external processor.

    Parallel image processor
    6.
    发明公开
    Parallel image processor 失效
    平行Bildverarbeitungsgerät。

    公开(公告)号：EP0189943A2

    公开(公告)日：1986-08-06

    申请号：EP86101338.1

    申请日：1986-01-31

    申请人： HITACHI, LTD.

    发明人： Miura, Shuuichi ,  Kobayashi, Yoshiki ,  Fukushima, Tadashi ,  Okuyama, Yoshiyuki ,  Katoh, Takeshi ,  Hirasawa, Kotaro ,  Asada, Kazuyoshi

    IPC分类号： G06F15/68

    CPC分类号： G06T5/20

    摘要： An LSI parallel image processor in which line buffers (20-i) and data-flow switching circuits (70) each requiring a larger amount of hardware in the prior art are incorporated into an LSI circuit, the image data delayed by the line buffers (20-i) is output from an image data output port (55), shift registers (31-i) each having a variable number of steps for preserving local image regions are intermittently shifted-in in accordance with applied clocks, and the contents of the shift registers (31-i) are sequentially read out.

    摘要翻译： LSI现有技术中需要较大硬件量的行缓冲器（20-i）和数据流切换电路（70）的LSI并行图像处理器被并入到LSI电路中，由行缓冲器 20-i）从图像数据输出端口（55）输出，每个具有可变数目的用于保存局部图像区域的移位寄存器（31-i）根据施加的时钟间歇地移入，并且内容 顺序地读出移位寄存器（31-i）。

    A peripheral apparatus for image memories
    7.
    发明公开
    A peripheral apparatus for image memories 失效
    对图像存储外围设备。

    公开(公告)号：EP0176801A2

    公开(公告)日：1986-04-09

    申请号：EP85111248.2

    申请日：1985-09-05

    申请人： HITACHI, LTD.

    发明人： Kobayashi, Yoshiki ,  Takenaga, Hiroshi ,  Katoh, Takeshi

    IPC分类号： G09G1/16

    CPC分类号： G09G5/39

    摘要： A peripheral apparatus for image memories can communicate image data with a memory assembly composed on n blocks (60-63) of a standard-type DRAM, whether DRAM is of page mode or of nibble mode. The apparatus comprises a read data processing unit (82) sending the data of selected one among n pixels read from the DRAM blocks in parallel to an external image/graphics processor (2), a write data processing unit (84) modifying the image data taken thereinto and writing the modified data in the DRAM blocks, a feedback data (86) processing unit writing the image data now on displaying into the DRAM blocks after a desired processing again, a display data processing unit (88) sending the data read from the DRAM blocks to a monitor for display and to the external processor (2) for the feedback processing, and a control unit (80) furnishing control signals to those processing units in response to instructions from the external processor.

    Parallel image processor
    9.
    发明公开
    Parallel image processor 失效
    并行图像处理器

    公开(公告)号：EP0189943A3

    公开(公告)日：1988-12-14

    申请号：EP86101338

    申请日：1986-01-31

    申请人： HITACHI, LTD.

    发明人： Miura, Shuuichi ,  Kobayashi, Yoshiki ,  Fukushima, Tadashi ,  Okuyama, Yoshiyuki ,  Katoh, Takeshi ,  Hirasawa, Kotaro ,  Asada, Kazuyoshi

    IPC分类号： G06F15/68

    CPC分类号： G06T5/20

    摘要： An LSI parallel image processor in which line buffers (20-i) and data-flow switching circuits (70) each requiring a larger amount of hardware in the prior art are incorporated into an LSI circuit, the image data delayed by the line buffers (20-i) is output from an image data output port (55), shift registers (31-i) each having a variable number of steps for preserving local image regions are intermittently shifted-in in accordance with applied clocks, and the contents of the shift registers (31-i) are sequentially read out.

    Image signal processor
    10.
    发明公开
    Image signal processor 失效
    图像信号处理设备。

    公开(公告)号：EP0118053A2

    公开(公告)日：1984-09-12

    申请号：EP84101305.5

    申请日：1984-02-08

    申请人： HITACHI, LTD.

    发明人： Fukushima, Tadashi ,  Kobayashi, Yoshiki ,  Okuyama, Yoshiyuki ,  Katoh, Takeshi ,  Kashioka, Seiji

    IPC分类号： G06F15/66

    CPC分类号： G06T1/20

    摘要： A high speed, multi-function and expandable image processing LSI (image signal processor) for realizing density image processing technique has been developed.
    An architecture of the image signal processor (ISP) which can process a density image having 256 tones at a video rate (256 x 256 image, 6MHz, non-interlace), allows expansion of a partial operation area (kernel) and can carry out various partial neighbourhood operation, is disclosed.
    The image signal processor (ISP) is a partial parallel type image processing LSI which carries out a parallel operation by using the same number of processor elements (PE's) as that of input pixel data used to produce one output pixel data.