据说用于读取集成MTL存储器的方法和在其中之前或期间读取操作中，线路能力和字线驱动器和位线驱动器，一读/写电路是本旁边排出的电路布置。 同时或以微小的时间延迟（T1）与字线（WL）的选择是两个相同的电流源（IRDO）由两个相应的下游的开关（S0和S1）到对应的位线（B0和B1）的装置接通。 其特征在于所述两个位线PNP晶体管（T1和T4）的两个喷射器与相同的电流供给。 在第二阶段（T2）的电流源（IRDO）再次关断，以这样的方式，第二时间阶段（τ2）的持续时间比所述位线PNP晶体管（T4）的存储时间常数（TE）实质上更大，则 与关断NPN晶体管（T3）连接到的小区。 连接到被连接在导通的NPN型晶体管单元（T2）的位线的PNP晶体管（T1）的有效存储时间常数（τSAT），比所述存储时间常数（.tau.e）大得多。 由于不同的时间常数（.tau.e和τSAT）第三阶段（T3）内的两个存储电荷（Q1和Q4）是不同的快速降解，由此产生一个非常快的和大的输出信号（ΔVBL= VS）。

Disclosed is a method and a circuit arrangement provided for reading an integrated MTL memory in which are discharged before or during a read operation, line capacities and in addition to the Wortieitungstreibern and the bit line drivers, a read / write circuit is present. Simultaneously or with a slight time delay (t1) with the selection of a word line (WL) are two identical current sources (IRDO) by means of two respective downstream switches (SO and S1) to the corresponding bit line (BO and B1) switched on. Characterized the two injectors of the two Bitieitungs PNP transistors (T1 and T4) are supplied with identical currents. in a second phase (t2) the current sources (IRDO) are switched off again, in such a way that the duration of the second time phase (t2) is substantially greater than the storage time constant _(T e) of the bit line PNP transistor (T4), the with the off NPN transistor (T3) is connected to a line. The effective storage time constant _(T SAT) of the bit line PNP transistors (T1) connected to the turned-on NPN Zelitransistor (T2) is connected, is substantially greater than the storage time constant (.tau.e). Due to the different time constants (.tau.e and RSAT) the two storage charges (Q1 and Q4) within the third phase (t3) are degraded at different rates, giving rapid and large output (AVBL = VS) is generated.