An error correcting system uses an error location polynominal defined by double correction BCH codes each consisting of the elements of Galois field GF(2m), thereby to generate error locations σ 1 and σ 2 and error patterns e, and e 2 . The system has a first data processing system (401) for performing only additions and multiplications to generate error locations σ 1 and σ 2 and a second data processing system (402) for performing only additions and mutiplica- tions to generate error patterns e 1 and e 2 . The first data processing system (401) comprises a syndrome generator (41), a memory (43), an arithmetic logic unit (44), registers (45A) to (45C), latch circuits (46A) to (46F), registers (47A) to (47F), adder circuits (48A) and (48B) and a zero detector (49). The second data processing system (402) comprises a gate circuit (50), latch circuits (46H) and (46G), an arithmetic logic unit (44), registers (45A) to (45C) and a memory (43).