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1.发明公开
公开(公告)号：EP0129223A3
公开(公告)日：1987-06-03
申请号：EP84106847
申请日：1984-06-15
Applicant: HITACHI, LTD.
Inventor： Nishimura, Keizo , Kobayashi, Masaharu , Okamoto, Hiroo , Noguchi, Takaharu , Arai, Takao , Shibuya, Toshifumi
CPC classification number: G11B20/1809
Abstract: A method of transmitting a digital signal in the form of successive signal frames containing codes for detecting and correcting errors of the digital signal for reducing degradation in the quality of the reproduced sound due to generation of the code errors in a digitized audio signal transmission system. An analog signal such as audio signal is sampled and subjected to A/D conversion. The sample word thus obtained is divided into a plurality of symbol elements Parity words for detecting and correcting code errors are added to every group of a predetermined number of the information symbols through interleave procedure before being transmitted The method includes steps of applying a first frame of symbols. taken one from each input channel and having a first arrangement state, to a first error-correcting code encoder (2) to generate a series of first parity words; delaying each of the symbols in the first frame and each of the first parity words by a respective different delay time in a unit of the sample word at a delay line (31 to provide a resulting second frame of symbols in a second arrangement state; applying the second frame of symbols to a second error-correcting code encoder (4) to generate a series of second parity words (P); and transmitting said second frame of symbols together with said second parity words.
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公开(公告)号：EP0127136A3
公开(公告)日：1988-01-13
申请号：EP84105937
申请日：1984-05-24
Applicant: Siemens Aktiengesellschaft , Philips Kommunikations Industrie AG , ANT Nachrichtentechnik GmbH
Inventor： Hessenmüller, Horst, Dipl.-Ing.
CPC classification number: H04B14/04
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公开(公告)号：EP0124906A3
公开(公告)日：1988-01-13
申请号：EP84105203
申请日：1984-05-08
Applicant: Siemens Aktiengesellschaft
Inventor： Strehl, Herbert, Dipl.-Ing.
CPC classification number: H04L1/0057 , H04J3/07 , H04J3/12
Abstract: Das Digitalsignal-Multiplexgerät wenigstens einen Mul tiplexer (1, 2) und wenigstens einen Demultiplexer (6, 7) für Pulsrahmen mit mehreren Nutzinformationskanälen. Im Sen deteil befindet sich ein Datensicherungscoder (3) und im Empfangsteil ein Datensicherungsdecoder (5). Der Datens icherungscoder (3) erzeugt einen Fehlersicherungscode und belegt mit der Fehlersicherungsinformation einen oder mehrere Nutzinformationskanäle oder ganzzahlige Teile wenigstens eines Nutzinformationskanals im Pulsrahmen. Diese werden empfangsseitig dem Datensicherungsdecoder (5) zugeführt, der Fehler in allen oder einzelnen Kanälen des übertragenen Zeitmultiplexsignals erkennt und korrigiert. Auf diese Weise können alle oder einzelne beispielsweise für die Datenübertragung vorgesehene Nutzinformationskanäle mit geringerer Bitfehlerquote übertragen, ohne dabei die genormten Hierarchiestufen der Übertragungssysteme zu verlassen.
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4.发明公开Digital information transmitting system and digital information receiving apparatus 失效数字信息发送系统和数字信息接收装置
公开(公告)号：EP0110352A3
公开(公告)日：1987-07-15
申请号：EP83111843
申请日：1983-11-25
Applicant: NIPPON HOSO KYOKAI , KABUSHIKI KAISHA TOSHIBA
Inventor： Kawai, Naoki , Yoshino, Takehiko , Endoh, Kenjiro , Kitagawa, Kazuo , Ohno, Kaiji
IPC: H04L01/10
CPC classification number: H04L1/004
Abstract: Second data (Y) for identifying valid data section (A21) and invalid data section (A22) of first data (X) is added the first data (X), transmitted, the invalid data section (A22) is detected according to the second data (Y) at receiving side, and the error of the invalid data section (A22) is forcibly corrected in accordance with a predetermined rule.
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公开(公告)号：EP0050434A3
公开(公告)日：1984-07-25
申请号：EP81304591
申请日：1981-10-05
Applicant: Honeywell Information Systems Inc.
Inventor： Holtey, Thomas O. , Noyes, Steven S. , Kelly, Richard P. , Raymond, James C.
CPC classification number: H04L1/0083 , G06F13/4226
Abstract: A communication device comprises a microprocessor which feeds bytes to a universal synchronous receiver transmitter (USRT) 88. The USRT transmits the data serially, signal C2TXSO+. On an underrun (USRT empty before next byte in), the USRT transmits a sequence of flag bytes (01111110) and generates an underrun signal C2TXTXU+. This signal is fed to transmit underrun logic 92, where a shift register 350 generates a 1 signal which lasts long enough to convert the first two 0's in the flag byte sequence to 1's by OR gate 354. A sequence of 8 to 13 1's is therefore generated prior to the flag bytes, this 1 sequence indicating an underrun condition.
Abstract translation: 通信设备包括将字节馈送到通用同步接收机发射机（USRT）88的微处理器.USRT以串行方式发射数据，信号C2TXSO +。 在欠载（USRT在下一个字节之前为空）之前，USRT发送一系列标志字节（01111110），并生成欠载信号C2TXTXU +。 该信号被馈送到发送欠载逻辑92，其中移位寄存器350产生持续足够长的1信号，以将标志字节序列中的前两个0转换为或门354。因此，8到13 1的序列是 在标志字节之前产生，该1序列指示欠载条件。
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Patent Agency Ranking
公开(公告)号：EP0092216A3
公开(公告)日：1984-02-22
申请号：EP83103733
申请日：1983-04-18
Applicant: Siemens Aktiengesellschaft
Inventor： Meyer, Fritz, Dr.-Ing.
CPC classification number: H04L1/247
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公开(公告)号：EP0067310A3
公开(公告)日：1984-02-15
申请号：EP82104116
申请日：1982-05-12
Applicant: International Business Machines Corporation
Inventor： Mueller, Mark Wayne , Parker, Thomas Shelton
CPC classification number: H04L5/1423 , H04L1/0083
Abstract: A communication adapter circuit (10) is connected to a processor through processor I/0 interface buses (12, 14). Data and control signals are provided through the buses (12, 14) to a timer circuit (18), a programmable peripheral interface circuit (20), an asynchronous and bisynchronous control circuit (22) and an SDLC/HDLC control circuit (24). Each of the control circuits (22, 24) includes parallel-to-serial and serial-to-parallel conversion circuitry. A clock select circuit (32) operates in conjunction with the timer circuit (18) and the programmable peripheral interface circuit (20) to establish a data transmission rate for the data flow through the adapter circuit (10). From the control circuits (22, 24) the data is transmitted through a modem interface bus (44) to a dual modem switch (56). From the switch (56) the data is transmitted to either an EIA RS 232 interface circuit (60) to a conventional modem or through a bus (64) to an internal modem. A phase locked loop circuit in the control circuit (24) generates a data clock signal on a line (33) for operation of the adapter circuit (0) in the bisynchronous protocol with a non-clock-generating modem.
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8.发明公开
公开(公告)号：EP0123322A3
公开(公告)日：1987-09-09
申请号：EP84104700
申请日：1984-04-26
Applicant: NEC CORPORATION
Inventor： Tomimitsu, Yasuharu
CPC classification number: G11B20/1809 , G11B20/12
Abstract: in an address indication circuit for use in indicating memory addresses of a random access memory to provide delays necessary for successive channels, channel addresses are determined relative to the memory addresses by assigning a reference number to a leading one of the channels and by successively accumulating the reference number and numbers determined for the delays to decide results of accumulation as the remaining channel addresses. The respective channel addresses are stored in a read-only memory (80) and added by an adder (83) to a base address variable at every time interval to provide memory addresses. When the memory addresses are equal in number to a preselected number, the base address may be produced by a counter (81) carrying out operation between zero and the preselected number less one. The adder adds the reference number to the base address modulo the preselected number.
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公开(公告)号：EP0151430A3
公开(公告)日：1987-08-26
申请号：EP85100645
申请日：1985-01-23
Applicant: HONEYWELL INC.
Inventor： Kozlik, Tony J.
CPC classification number: H04L12/417 , H04L1/0083 , H04L25/4904
Abstract: A detector of predetermined patterns of Manchester encoded data signals (PRICHL) in which the voltage levels of the half-bit cells of "n" sequential Manchester bit cells, where "n" is an integer greater than zero, are clocked into a shift register (12-1, 12-2), the pattern of 2 "n" voltage levels of 2 "n" half-bit cells of the "n" sequential Manchester bit cells stored in the register at any given time are examined by a programmable logic array (18) which produces an output signal when the pattern of outputs of the shift register corresponds to the predetermined patterns (Fig. 1).
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公开(公告)号：EP0118763A3
公开(公告)日：1987-07-22
申请号：EP84101290
申请日：1984-02-08
Applicant: HITACHI, LTD.
Inventor： Takasaki, Yoshitaka , Yamashita, Kiichi , Takahashi, Yasushi
Abstract: A method of searching fault locations which is-employed in a transmission system comprising a transmitting terminal (1) having a transmitter (2) for transmitting a digital signal; a receiving terminal (5) having a receiver (8) for receiving the digital signal; a plurality of repeaters (4, 4, ...) which are placed between the transmitting and receiving terminals, and each of which receives and amplifies the digital signal from a preceding repeater section and deliver it to a subsequent repeater section; and a plurality of transmission lines (3, 3, ...) for connecting the transmitter with the first repeater, the repeaters with each other and the final repeater with each other and the final repeater with the receiver, respectively. This method comprises the steps of coding an orginal signal to be transmitted in terms of two kinds of error detecting codes at the transmitting terminal to send out them from the transmitter; detecting an error of a received signal using one of the two kinds of error detecting codes at each repeater thereby to measure the error rate occurred at one repeater section corresponding to each repeater; recording a decoded received signal using the error detecting code employed to detect the error, and delivering it to a subsequent repeater section; and transmitting signals each of which represents the error rate at each repeater section measured at each repeater, to the transmitting terminal or receiving terminal.
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