A central execution pipeline unit, for initiating the execution of instructions by a synchronous CPU, operates in 6 stages or cycles. Instructions are obtained in program order from an instruction fetch unit of the CPU. Stage 1: the address information of an instruction is used to form the carries and sums of an effective address and to initiate the formation of a virtual address; and the instruction field is decoded to produce memory command signals and data alignment signals. Stage 2: the formation of the effective and virtual address is completed, and the word address portion of the virtual address is transmitted to the cache unit of the CPU; memory command signals are sent to the cache units; the instruction field is converted to an execution code for one of a pluralify of execution units; and the execution unit to execute the code is designated. Stage 3: the virtual address is converted to a physical address (real page number) which is transmitted to a cache unit; and the execution code is sent to the designated execution unit, except that if the execution unit is the central unit, the execution code for that unit is converted into execution unit control signals. Stage 4: data alignment control signals are sent to a distributor, of the central execution pipeline unit, which aligns the data. Stage 5: the addressed execution unit is enabled to receive the addressed operand or target word from the distributor, and the instruction field of the instruction is transmitted to the collector unit of the CPU. Stage 6: results of the execution of an instruction by the central execution unit are loaded into a results stack and indicator registers of the central execution pipeline unit are updated.