公开(公告)号：EP0106664A2

公开(公告)日：1984-04-25

申请号：EP83306186.4

申请日：1983-10-13

Applicant: Honeywell Information Systems Inc.

Inventor： Wilhite, John E. ,  Trubisky, Leonard G. ,  Shelly, William A. ,  Circello, Joseph C. ,  Guenthner, Russell W.

IPC: G06F9/38

CPC classification number: G06F9/3867

Abstract: A central execution pipeline unit, for initiating the execution of instructions by a synchronous CPU, operates in 6 stages or cycles. Instructions are obtained in program order from an instruction fetch unit of the CPU. Stage 1: the address information of an instruction is used to form the carries and sums of an effective address and to initiate the formation of a virtual address; and the instruction field is decoded to produce memory command signals and data alignment signals. Stage 2: the formation of the effective and virtual address is completed, and the word address portion of the virtual address is transmitted to the cache unit of the CPU; memory command signals are sent to the cache units; the instruction field is converted to an execution code for one of a pluralify of execution units; and the execution unit to execute the code is designated. Stage 3: the virtual address is converted to a physical address (real page number) which is transmitted to a cache unit; and the execution code is sent to the designated execution unit, except that if the execution unit is the central unit, the execution code for that unit is converted into execution unit control signals. Stage 4: data alignment control signals are sent to a distributor, of the central execution pipeline unit, which aligns the data. Stage 5: the addressed execution unit is enabled to receive the addressed operand or target word from the distributor, and the instruction field of the instruction is transmitted to the collector unit of the CPU. Stage 6: results of the execution of an instruction by the central execution unit are loaded into a results stack and indicator registers of the central execution pipeline unit are updated.

Abstract translation: 用于启动由同步CPU执行指令的中央执行流水线单元以6个阶段或周期运行。 从CPU的指令提取单元以程序顺序获取指令。 阶段1：指令的地址信息用于形成有效地址的载入和和，并启动虚拟地址的形成; 并且指令字段被解码以产生存储器命令信号和数据对准信号。 阶段2：完成有效和虚拟地址的形成，并将虚拟地址的字地址部分发送到CPU的高速缓存单元; 存储器命令信号被发送到高速缓存单元; 指令字段被转换为执行单元的多个的一个的执行代码; 并且指定执行代码的执行单元。 阶段3：将虚拟地址转换为发送到高速缓存单元的物理地址（实际页码）; 并且执行代码被发送到指定执行单元，除了如果执行单元是中央单元，则该单元的执行代码被转换为执行单元控制信号。 阶段4：数据对齐控制信号被发送到中央执行流水线单元的分配器，其对准数据。 阶段5：寻址执行单元能够从分配器接收寻址的操作数或目标字，指令的指令字段被发送到CPU的收集器单元。 阶段6：由中央执行单元执行指令的结果被加载到结果堆栈中，中央执行流水线单元的指示符寄存器被更新。

公开(公告)号：EP0106670B1

公开(公告)日：1988-06-08

申请号：EP83306194.8

申请日：1983-10-13

Applicant: Honeywell Information Systems Inc.

Inventor： Guenthner, Russell W. ,  Trubisky, Leonard G. ,  Circello, Joseph C. ,  Edgington, Gregory C.

IPC: G06F9/38

CPC classification number: G06F9/3885 ,  G06F9/3863

公开(公告)号：EP0106664B1

公开(公告)日：1988-08-31

申请号：EP83306186.4

申请日：1983-10-13

Applicant: Honeywell Information Systems Inc.

Inventor： Wilhite, John E. ,  Trubisky, Leonard G. ,  Shelly, William A. ,  Circello, Joseph C. ,  Guenthner, Russell W.

IPC: G06F9/38

CPC classification number: G06F9/3867

公开(公告)号：EP0106670A3

公开(公告)日：1986-04-16

申请号：EP83306194

申请日：1983-10-13

Applicant: Honeywell Information Systems Inc.

Inventor： Guenthner, Russell W. ,  Trubisky, Leonard G. ,  Circello, Joseph C. ,  Edgington, Gregory C.

IPC: G06F09/38

CPC classification number: G06F9/3885 ,  G06F9/3863

Abstract: A collector for the results of a pipelined central processing unit of a digital data processing system. The processor has a plurality of execution units 24, 26, 28, 30, with each execution unit executing a different set of instructions of the instruction repertoire of the processor. The execution units execute instructions issued to them in order of issuance by the pipeline 12 and in parallel. As instructions are issued to the execution units, the operation code identifying each instruction is also issued in program order to an instruction execution queue 18 of the collector. The results of the execution of each instruction by an execution unit are stored in a result stack 38, 40, 42, 44 associated with each execution unit. Collector control 46 causes the results of the execution of instructions to program visible registers to be stored in a master safe store register 48 in program order which is determined by the order of instructions stored in the instruction execution stack on a first-in, first-out basis. The collector also issues write commands to write results of the execution of instructions into memory in program order via a store stack 50.

公开(公告)号：EP0106664A3

公开(公告)日：1986-08-20

申请号：EP83306186

申请日：1983-10-13

Applicant: Honeywell Information Systems Inc.

Inventor： Wilhite, John E. ,  Trubisky, Leonard G. ,  Shelly, William A. ,  Circello, Joseph C. ,  Guenthner, Russell W.

IPC: G06F09/38

CPC classification number: G06F9/3867

Abstract: A central execution pipeline unit, for initiating the execution of instructions by a synchronous CPU, operates in 6 stages or cycles. Instructions are obtained in program order from an instruction fetch unit of the CPU. Stage 1: the address information of an instruction is used to form the carries and sums of an effective address and to initiate the formation of a virtual address; and the instruction field is decoded to produce memory command signals and data alignment signals. Stage 2: the formation of the effective and virtual address is completed, and the word address portion of the virtual address is transmitted to the cache unit of the CPU; memory command signals are sent to the cache units; the instruction field is converted to an execution code for one of a pluralify of execution units; and the execution unit to execute the code is designated. Stage 3: the virtual address is converted to a physical address (real page number) which is transmitted to a cache unit; and the execution code is sent to the designated execution unit, except that if the execution unit is the central unit, the execution code for that unit is converted into execution unit control signals. Stage 4: data alignment control signals are sent to a distributor, of the central execution pipeline unit, which aligns the data. Stage 5: the addressed execution unit is enabled to receive the addressed operand or target word from the distributor, and the instruction field of the instruction is transmitted to the collector unit of the CPU. Stage 6: results of the execution of an instruction by the central execution unit are loaded into a results stack and indicator registers of the central execution pipeline unit are updated.

公开(公告)号：EP0106671A3

公开(公告)日：1986-07-16

申请号：EP83306196

申请日：1983-10-13

Applicant: Honeywell Information Systems Inc.

Inventor： Guenthner, Russell W. ,  Marietta, Kala J. ,  Presley-Nelson, Gary R. ,  Shelly, William A.

IPC: G06F09/38

CPC classification number: G06F9/3806 ,  G06F9/322 ,  G06F9/3889

Abstract: Prefetching instructions for a pipelined CPU. A TIP (transfer and indirect prediction) table 42 predicting the target address of transfer and indirect instructions based on past history of the execution of those instructions. The prefetch mechanism forms instruction addresses and fetches instructions in parallel with the execution of previously fetched instructions by a central execution pipeline unit (CEPU) 12 of the CPU. As instructions are prefetched, the TIP table is checked to determine the past history of those instructions. If no transfers or indirects are found, the prefetch proceeds sequentially. If transfer or indirect instructions are found, then the prefetch uses information in the TIP table to begin fetching the target instruction(s). The target addresses are predicted so that in the usual case instructions following a transfer can be executed at a rate of 1 instruction per pipeline cycle regardless of the pipeline depth or the frequency of transfers. Instructions are fetched 2 words at a time, so that the instruction fetch unit (IFU) 10 can stay ahead of the CEPU. An instruction stack 20 buffers double words of instructions fetched by the IFU while waiting for execution by the CEPU. The TIP table is updated based upon the actual execution of instructions by the CEPU, and the correctness of the TIP table predictions is checked during execution of every instruction.

公开(公告)号：EP0106670A2

公开(公告)日：1984-04-25

申请号：EP83306194.8

申请日：1983-10-13

Applicant: Honeywell Information Systems Inc.

Inventor： Guenthner, Russell W. ,  Trubisky, Leonard G. ,  Circello, Joseph C. ,  Edgington, Gregory C.

IPC: G06F9/38

CPC classification number: G06F9/3885 ,  G06F9/3863

Abstract: A collector for the results of a pipelined central processing unit of a digital data processing system. The processor has a plurality of execution units 24, 26, 28, 30, with each execution unit executing a different set of instructions of the instruction repertoire of the processor. The execution units execute instructions issued to them in order of issuance by the pipeline 12 and in parallel. As instructions are issued to the execution units, the operation code identifying each instruction is also issued in program order to an instruction execution queue 18 of the collector. The results of the execution of each instruction by an execution unit are stored in a result stack 38, 40, 42, 44 associated with each execution unit. Collector control 46 causes the results of the execution of instructions to program visible registers to be stored in a master safe store register 48 in program order which is determined by the order of instructions stored in the instruction execution stack on a first-in, first-out basis. The collector also issues write commands to write results of the execution of instructions into memory in program order via a store stack 50.