公开(公告)号：EP0056525B1

公开(公告)日：1989-10-18

申请号：EP81306019.1

申请日：1981-12-22

Applicant: Honeywell Information Systems Inc.

Inventor： Tague, Steven A. ,  Negi, Virendra S.

IPC: G06F7/52

CPC classification number: G06F7/4917

公开(公告)号：EP0178670A3

公开(公告)日：1987-09-30

申请号：EP85113206

申请日：1985-10-17

Applicant: Honeywell Information Systems Inc.

Inventor： Joyce, Thomas F. ,  Kelly, Richard P.

IPC: G06F11/14

CPC classification number: G06F11/141 ,  G06F11/1008

Abstract: A method and apparatus for a microinstruction controlled unit to recover from a read error in reading microinstructions from a control store. The method provides for the overlapping of the execution of a current microinstruction while the next microinstruction is being addressed and read from the control store. Execution of the current microinstru- tion is begun before it is known whether or not it was read without error. The apparatus provides for aborting the execution of the current microinstruction with the read error and the next microinstruction. During the aborted execution of the next microinstruction, the current microinstruction is reread from the control store and then executed while the next microinstruction is being reread. The execution of microinstructions is aborted in a manner that does not alter the state of the microinstruction controlled unit beyond the point that would inhibit the re-execution of the aborted microinstructions.

公开(公告)号：EP0081336B1

公开(公告)日：1987-03-18

申请号：EP82306382.1

申请日：1982-12-01

Applicant: Honeywell Information Systems Inc.

Inventor： Stanley, Philip E. ,  Woods, William E. ,  Lemay, Richard A. ,  Cushing, David E.

IPC: G06F9/30 ,  G01F5/00

CPC classification number: G06F9/30032 ,  G06F9/30167

公开(公告)号：EP0107449A3

公开(公告)日：1987-01-07

申请号：EP83306195

申请日：1983-10-13

Applicant: Honeywell Information Systems Inc.

Inventor： Circello, Joseph C.

IPC: G06F09/44 ,  G06F09/46

CPC classification number: G06F12/109

Abstract: In a data processing system including a central processing unit capable of operation with a plurality of operating systems, a VMSM (virtual memory and security manager) unit for producing a composite decor descriptor from a plurality of possible decor descriptor formats. The VMSM unit includes an input buffer unit 515, a control unit 510 to analyze an incoming DATA and provide appropriate control signals, a reconfiguration unit 513 for reformatting the plurality of descriptor formats into a composite format, a descriptor fetch unit 512 for retrieving a descriptor when the signals applied to the VMSM unit contain a descriptor address, and a descriptor master copy unit 514 which contains a copy of the descriptors stored in the addressing apparatus.

公开(公告)号：EP0131277A3

公开(公告)日：1986-06-11

申请号：EP84107914

申请日：1984-07-06

Applicant: Honeywell Information Systems Inc.

Inventor： Hooker, Lane K. ,  Howell, Thomas H. ,  Ferrell, Charles W.

IPC: G06F12/08

CPC classification number: G06F12/0817 ,  G06F12/084

Abstract: A multiple processor computer system features a store-into cache arrangement wherein each processor unit of the system has its own unique cache memory unit. Data operated upon by any one of the processor units is stored in the cache memory associated with that processor unit. When a thus modified block of data is required by another one of the processor units, the requested data is transferred directly to the requesting processor unit without having to first transfer the data to a shared main memory. Provision is also made for transferring data, under prescribed conditions from a cache to the main memory, but not as a precondition for transfer to a requesting processor.

Abstract translation: 多处理器计算机系统具有存储到高速缓存布置，其中系统的每个处理器单元具有其自己的唯一高速缓冲存储器单元。 由任何一个处理器单元操作的数据被存储在与该处理器单元相关联的高速缓冲存储器中。 当另一个处理器单元需要如此修改的数据块时，将所请求的数据直接传送到请求处理器单元，而不必首先将数据传送到共享的主存储器。 还规定了在规定的条件下将数据从缓存传送到主存储器，但不作为转移到请求处理器的前提条件。

公开(公告)号：EP0107447A3

公开(公告)日：1986-04-16

申请号：EP83306191

申请日：1983-10-13

Applicant: Honeywell Information Systems Inc.

Inventor： Wilhite, John E. ,  Shelly, William A.

IPC: G06F09/38

CPC classification number: G06F9/3867

Abstract: A distributor for the central execution pipeline unit of a central processor, in a data processing system, which has a plurality of execution units. The distributor serves as a communications center by which machine words, such as operands, are transmitted primarily from the cache unit of the central processor unit to execution units and the instruction fetch unit of the central processor unit. Some machine words are transmitted directly from the collector unit to selected units and others are transmitted after being stored in the data register 12 of the distributor. Machine words stored in the data register can be realigned if required by an instruction by character or word alignment switches 26, 28. The aligned words are then stored in the data register 1 prior to their being transmitted to units (CEU, BINAU, DECCU, VMSM) of the central processor. Other sources of signals transmitted by the distributor are the collector unit and registers of the distributor containing the effective address of a target word (REA) as calculated by the central execution pipeline unit, as well as copies of machine words in key registers, the A/Q registers, of certain of the execution units.

公开(公告)号：EP0082616A3

公开(公告)日：1985-08-21

申请号：EP82306376

申请日：1982-12-01

Applicant: Honeywell Information Systems Inc.

Inventor： Dries, Michael F. ,  Gurnee, Mark N.

IPC: H01L27/14 ,  H01L29/78

CPC classification number: H01L29/76808 ,  H01L27/14868 ,  H01L27/14881

Abstract: Apparatus for compressing an electrical input signal so as to accommodate a large dynamic range of the signal without loss of information represented by the signal, the apparatus comprising first, second and third (12, 14, 16) storage means for receiving the input signal; a gate (18) coupled between the second and third storage means so as to selectively inhibit the transfer of the signal from the second storage means to the third storage means; means (24. 28) coupling the third storage means to a receiving device; and means, including the gate (18), for enabling substantially all of the signal to be received by the receiving device for low levels of the signal, and for enabling only a portion of the signal to be received by the receiving device for other than low levels of the signal.

公开(公告)号：EP0114523A3

公开(公告)日：1985-05-02

申请号：EP83307916

申请日：1983-12-22

Applicant: Honeywell Information Systems Inc.

Inventor： Boudreau, Daniel A. ,  Salas, Edward R. ,  Sandini, James M.

IPC: G06F03/04

CPC classification number: G06F13/37 ,  G06F13/378

Abstract: A bus for coupling a plurality of units in a data processing system for the transfer of information therebetween. The units are coupled in a priority arrangement which is distributed, thereby providing priority logic in each of the units and allowing bus transfer cycles to be generated in an asynchronous manner. Priority is normally granted on the basis of physical position on the bus, highest priority being given to the first unit on the bus and lowest priority being given to the last unit on the bus. Each of the units includes priority logic which includes logic elements for requesting a bus cycle, such request being granted if no other higher priority unit has also requested a bus cycle. The request for and an indication of the grant of the bus cycle are stored in each unit so requesting and being granted the bus cycle respectively; only one such unit is capable of having the grant of a bus cycle at any given time, whereas any number of such units may have their requests pending at any particular time. The present invention provides a modification to the priority logic which allows a lowest priority unit to be physically positioned at other than the last unit position on the common bus.

公开(公告)号：EP0072179A3

公开(公告)日：1985-01-23

申请号：EP82304086

申请日：1982-08-03

Applicant: Honeywell Information Systems Inc.

Inventor： Webster, Marvin K. ,  Flynn, Richard T. ,  Porter, Marion G. ,  Seminsky, George M.

IPC: G06F13/00 ,  G11C09/06

CPC classification number: G06F12/0808

Abstract: A cache memory comprises a directory 202 and a data store 201. The n-bit portion of a desired address from an associated CPU selects a location in directory 202, and the m-bit address portions in the 4 levels I to IV of that location are compared at 203 with the m-bit portion of the desired address. On a match, the corresponding level of the corresponding location of the data store 201 is accessed to access the desired word. The cache words should mirror the contents of the main memory, but the latter may be changed by e.g. another CPU or an IOC, and the resulting invalid addresses must be cleared from the cache memory. This is done by searching the directory 202 for an invalid address during the second half of a cache cycle, after the directory has been searched to determine whether the desired word is in the cache and while that desired word is being accessed in the cache store 201. If an invalid address is found, the second half of the next cache cycle is used to clear it from the cache, by resetting the full/empty indicator in the directory control portion C for that level and that location.

公开(公告)号：EP0106664A2

公开(公告)日：1984-04-25

申请号：EP83306186.4

申请日：1983-10-13

Applicant: Honeywell Information Systems Inc.

Inventor： Wilhite, John E. ,  Trubisky, Leonard G. ,  Shelly, William A. ,  Circello, Joseph C. ,  Guenthner, Russell W.

IPC: G06F9/38

CPC classification number: G06F9/3867

Abstract: A central execution pipeline unit, for initiating the execution of instructions by a synchronous CPU, operates in 6 stages or cycles. Instructions are obtained in program order from an instruction fetch unit of the CPU. Stage 1: the address information of an instruction is used to form the carries and sums of an effective address and to initiate the formation of a virtual address; and the instruction field is decoded to produce memory command signals and data alignment signals. Stage 2: the formation of the effective and virtual address is completed, and the word address portion of the virtual address is transmitted to the cache unit of the CPU; memory command signals are sent to the cache units; the instruction field is converted to an execution code for one of a pluralify of execution units; and the execution unit to execute the code is designated. Stage 3: the virtual address is converted to a physical address (real page number) which is transmitted to a cache unit; and the execution code is sent to the designated execution unit, except that if the execution unit is the central unit, the execution code for that unit is converted into execution unit control signals. Stage 4: data alignment control signals are sent to a distributor, of the central execution pipeline unit, which aligns the data. Stage 5: the addressed execution unit is enabled to receive the addressed operand or target word from the distributor, and the instruction field of the instruction is transmitted to the collector unit of the CPU. Stage 6: results of the execution of an instruction by the central execution unit are loaded into a results stack and indicator registers of the central execution pipeline unit are updated.

Abstract translation: 用于启动由同步CPU执行指令的中央执行流水线单元以6个阶段或周期运行。 从CPU的指令提取单元以程序顺序获取指令。 阶段1：指令的地址信息用于形成有效地址的载入和和，并启动虚拟地址的形成; 并且指令字段被解码以产生存储器命令信号和数据对准信号。 阶段2：完成有效和虚拟地址的形成，并将虚拟地址的字地址部分发送到CPU的高速缓存单元; 存储器命令信号被发送到高速缓存单元; 指令字段被转换为执行单元的多个的一个的执行代码; 并且指定执行代码的执行单元。 阶段3：将虚拟地址转换为发送到高速缓存单元的物理地址（实际页码）; 并且执行代码被发送到指定执行单元，除了如果执行单元是中央单元，则该单元的执行代码被转换为执行单元控制信号。 阶段4：数据对齐控制信号被发送到中央执行流水线单元的分配器，其对准数据。 阶段5：寻址执行单元能够从分配器接收寻址的操作数或目标字，指令的指令字段被发送到CPU的收集器单元。 阶段6：由中央执行单元执行指令的结果被加载到结果堆栈中，中央执行流水线单元的指示符寄存器被更新。