A read only memory in which portion of an address area thereof is replaced with that of another memory comprises at least one address decoding output circuit (12) with a read only memory portion (13). The address decoding output circuit (12) is formed to be programmable at the same time as the read only memory portion. Thus, an apparatus having this read only memory can be miniaturized and have a low power consumption, and the process of producing a system including this read only memory is simplified.