公开(公告)号：EP2122631A1

公开(公告)日：2009-11-25

申请号：EP07719435.5

申请日：2007-03-29

申请人： Sidense Corp.

发明人： KURJANOWICZ, Wlodek ,  SMITH, Steven

IPC分类号： G11C17/18 ,  G11C17/08 ,  G11C17/16

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L21/28211 ,  H01L23/5252 ,  H01L27/10 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.

公开(公告)号：EP1367596A1

公开(公告)日：2003-12-03

申请号：EP03253060.2

申请日：2003-05-16

申请人： Hewlett-Packard Company

发明人： Perlov, Craig M. ,  Forrest, Stephen

IPC分类号： G11C17/06 ,  G11C17/08 ,  G11C17/14 ,  G11C17/16

CPC分类号： H01L27/285 ,  B82Y10/00 ,  G11C13/0009 ,  G11C13/0014 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/1021 ,  H01L51/0053 ,  H01L51/0078 ,  H01L51/0595

摘要： A donor/acceptor-organic-junction sheet (606) employed within an electronic memory array (118) of a cross-point diode memory. The donor/acceptor-organic-junction sheet (606) is anistropic with respect to flow of electrical current and is physically unstable above a threshold current. Thus, the volume of the donor/acceptor-organic-junction sheet (206) between a row line (602) and column line (604) at a two-dimensional memory array grid point serves both as the diode component (210) and as the fuse component (208) of a diode-and-fuse memory element and is electrically insulated from similar volumes of the donor/acceptor-organic-junction sheet between neighboring grid point intersections.

摘要翻译： 在交叉点二极管存储器的电子存储器阵列（118）内采用的施主/受体 - 有机结合片（606）。 供体/受体 - 有机结合片（606）相对于电流流动是无捻的，并且在阈值电流之上物理上是不稳定的。 因此，在二维存储器阵列栅极点处的行线（602）和列线（604）之间的施主/受体 - 有机结合片（206）的体积用作二极管组件（210）和二极管组件 二极管和熔丝存储器元件的熔丝部件（208），并且与相邻网格点交点处的施主/受体 - 有机结合片的类似体积电绝缘。

公开(公告)号：EP1436815A4

公开(公告)日：2007-04-11

申请号：EP02759714

申请日：2002-09-17

申请人： KILOPASS TECHNOLOGIES INC

发明人： PENG JACK ZEZHONG

IPC分类号： G11C17/08 ,  G11C17/16 ,  G11C11/56 ,  G11C29/50 ,  H01L21/8246 ,  H01L23/525 ,  H01L27/10 ,  H01L27/112

CPC分类号： H01L27/11206 ,  G11C11/5692 ,  G11C17/16 ,  G11C29/50 ,  G11C2029/5006 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory cell (300) having a data storage element (115) constructed around an ultra-thin dielectric (312) is used to store information by stressing the ultra-thin dielectric (312) into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell (300). The memory cell (300) is read by sensing the current drawn by the cell (300). A suitable ultra-thin dielectric (312) is high quality gate oxide of about 50 Å thickness or less.

公开(公告)号：EP0284091A2

公开(公告)日：1988-09-28

申请号：EP88104847.4

申请日：1988-03-25

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Shimamune, Yuji

IPC分类号： G11C7/00 ,  G11C17/08

CPC分类号： G11C16/28 ,  G11C7/062 ,  G11C16/06

摘要： A nonvolatile semiconductor memory device having a bit-line potential amplifying circuit (2) for amplifying the data potential read from a selected one of memory cells (MC) and a dummy bit-line potential amplifying circuit (6) for amplifying the data potential read from a dummy cell (DC). These amplifying circuits (2, 6) are of the same structure. The bit-line potential amplifying circuit (2) comprises a first MOS transistor (Q1) of N-channel type for clamping the bit-line poten­tial, a second MOS transistor (Q3) of the N-channel type for amplifying the bit-line potential, and a third MOS transistor (Q2) of an N-channel type functioning as a load of the second MOS transistor (Q3). The dummy bit-­line potential amplifying circuit (6) comprises a fourth MOS transistor (Q12) of the N-channel type for clamping the dummy bit-line potential, a fifth MOS transistor (Q14) of the N-channel type for amplifying the dummy bit-line potential, and a sixth MOS transistor (Q13) of the P-channel type functioning as a load of the fifth MOS transistor (Q14). The fifth MOS transistor (Q14) has the same element size as the second MOS transistor (Q3), and the sixth MOS transistor (Q13) has the same element size as the third MOS transistor (Q2). In addi­tion, the fourth MOS transistor (Q12) is driven by a current more readily than the first MOS transistor (Q1).

摘要翻译： 一种非易失性半导体存储器件，具有用于放大从存储单元（MC）中选定的一个读出的数据电位的位线电位放大电路（2）和用于放大数据电位读取的伪位线电位放大电路（6） 来自虚拟单元（DC）。 这些放大电路（2,6）具有相同的结构。 位线电位放大电路（2）包括用于钳位位线电位的N沟道型的第一MOS晶体管（Q1），用于放大位线的N沟道型的第二MOS晶体管（Q3） 电位和用作第二MOS晶体管（Q3）的负载的N沟道型的第三MOS晶体管（Q2）。 虚拟位线电位放大电路（6）包括用于钳位虚拟位线电位的N沟道型的第四MOS晶体管（Q12），用于放大虚拟位线电位的N沟道型的第五MOS晶体管（Q14） 伪位线电位以及用作第五MOS晶体管（Q14）的负载的P沟道型的第六MOS晶体管（Q13）。 第五MOS晶体管（Q14）具有与第二MOS晶体管（Q3）相同的元件尺寸，并且第六MOS晶体管（Q13）具有与第三MOS晶体管（Q2）相同的元件尺寸。 此外，第四MOS晶体管（Q12）由比第一MOS晶体管（Q1）更容易的电流驱动。

公开(公告)号：EP0254602B1

公开(公告)日：1992-10-07

申请号：EP87401164.6

申请日：1987-05-22

申请人： FUJITSU LIMITED

发明人： Kasa, Yasushi

IPC分类号： G06F12/06 ,  G11C17/08

CPC分类号： G11C17/08 ,  G06F12/0638 ,  Y02D10/13

摘要： A read only memory in which portion of an address area thereof is replaced with that of another memory comprises at least one address decoding output circuit (12) with a read only memory portion (13). The address decoding output circuit (12) is formed to be programmable at the same time as the read only memory portion. Thus, an apparatus having this read only memory can be miniaturized and have a low power consumption, and the process of producing a system including this read only memory is simplified.

公开(公告)号：EP0140368B1

公开(公告)日：1991-12-27

申请号：EP84113053.7

申请日：1984-10-30

申请人： NEC CORPORATION

发明人： Natsui, Yoshinobu ,  Mayumi, Hiroshi

IPC分类号： G11C29/00 ,  G11C17/08 ,  H01L27/10

CPC分类号： H01L27/1026 ,  G11C17/08 ,  G11C29/04 ,  G11C29/08 ,  G11C29/24

公开(公告)号：EP0254602A3

公开(公告)日：1990-05-02

申请号：EP87401164.6

申请日：1987-05-22

申请人： FUJITSU LIMITED

发明人： Kasa, Yasushi

IPC分类号： G06F12/06 ,  G11C17/08

CPC分类号： G11C17/08 ,  G06F12/0638 ,  Y02D10/13

摘要： A read only memory in which portion of an address area thereof is replaced with that of another memory comprises at least one address decoding output circuit (12) with a read only memory portion (13). The address decoding output circuit (12) is formed to be programmable at the same time as the read only memory portion. Thus, an apparatus having this read only memory can be miniaturized and have a low power consumption, and the process of producing a system including this read only memory is simplified.

公开(公告)号：EP3413315A1

公开(公告)日：2018-12-12

申请号：EP16888851.9

申请日：2016-02-18

申请人： Sichuan Kiloway Electronics Inc.

发明人： PENG, Jack Z. ,  MAO, Junhua ,  LIAO, Xuyang

IPC分类号： G11C17/16 ,  G11C17/08 ,  G11C17/12 ,  G11C17/14

CPC分类号： G11C17/16 ,  G11C17/08 ,  G11C17/12 ,  G11C17/123 ,  G11C17/14

摘要： A high-reliability one-time programmable memory adopting series high voltage partition, which relates to integrated circuit technology and comprises a first MOS tube (1), a second MOS tube (2) and an anti-fuse element (4), wherein a gate end of the first MOS tube (1) is connected to a second connecting line (WS), a first connecting end of the first MOS tube is connected to a gate end of the second MOS tube (2) and a voltage limiting device (3), and a second connecting end of the first MOS tube is connected to a third connecting line (BL); a first connecting end of the second MOS tube (2) is connected to a fourth connecting line (BR), a second connecting end of the second MOS tube is connected to the third connecting line (BL), and a gate end of the second MOS tube is connected to the voltage limiting device (3) and the second connecting end of the first MOS tube (1). The high-reliability one-time programmable memory adopting series high voltage partition further comprises the voltage limiting device (3), which comprises a control end and two connecting ends, wherein the control end is connected to a control signal line (WB), one connecting end is connected to a first connecting line (WP) through the anti-fuse device (4), and the other connecting end is connected to the gate end of the second MOS tube (2). In this way, the problem in the prior art that a device of a critical path is damaged and degraded due to high voltage pulse is solved, and possible hidden leakage troubles are avoided.

公开(公告)号：EP0945872B1

公开(公告)日：2006-05-31

申请号：EP99103413.3

申请日：1999-02-22

申请人： Infineon Technologies AG

发明人： Schmitt-Landsiedel, Doris, Prof. ,  von Basse, Paul-Werner ,  Thewes, Roland, Dr. ,  Bollu, Michael, Dr.

IPC分类号： G11C16/10 ,  G11C17/08

CPC分类号： G11C16/10

公开(公告)号：EP1643675A1

公开(公告)日：2006-04-05

申请号：EP05017238.6

申请日：2005-08-08

申请人： Broadcom Corporation

发明人： Buer, Mark

IPC分类号： H04L9/00 ,  G11C17/08 ,  G06F12/14

CPC分类号： G06F21/72 ,  G06F21/85 ,  G06Q20/3829 ,  H04L9/0897 ,  H04L63/0428 ,  H04L63/06 ,  H04L63/0853

摘要： A stateless hardware security module may communicate with other devices via a secure communication channel.
As a result, sensitive information such as cryptographic keys and data may be securely routed between the client device and another device. The stateless hardware security module may support a limited set of key management operations to facilitate routing of information between the client device and another device. However, the stateless hardware security module does not need to maintain state information for the keys it maintains and/or uses. As a result the stateless hardware security module may be advantageously integrated into a variety of client devices. A stateless hardware security module may support receiving keys in a secure manner from another device and storing and using these keys within a secure boundary. A stateless hardware security module may support generating a private/public key pair within a secure boundary, maintaining the private key within the secure boundary, and exporting the public key to an authenticating entity. The stateless security module may be implemented using a single-poly process, etc. In some embodiments the ability to use any process results from the use of an improved type of one-time programmable memory.

摘要翻译： 无状态硬件安全模块可以经由安全通信信道与其他设备进行通信。 结果，可以在客户端设备和另一设备之间安全地路由诸如加密密钥和数据的敏感信息。 无状态硬件安全模块可以支持有限的一组密钥管理操作，以便于在客户端设备和另一个设备之间路由信息。 然而，无状态硬件安全模块不需要维护其维护和/或使用的密钥的状态信息。 因此，无状态硬件安全模块可以有利地集成到各种客户端设备中。 无状态硬件安全模块可以以安全的方式支持从另一设备接收密钥，并在安全边界内存储和使用这些密钥。 无状态硬件安全模块可以支持在安全边界内生成私钥/公钥对，将私钥保持在安全边界内，并将公开密​​钥导出到认证实体。 无状态安全模块可以使用单聚合过程等来实现。在一些实施例中，使用任何处理的能力来自使用改进型的一次性可编程存储器。