-
1.发明授权
公开(公告)号：EP1118937B1
公开(公告)日：2003-10-22
申请号：EP01109451.3
申请日：1993-06-25
Applicant: FUJITSU LIMITED
Inventor： Akaogi, Takao , Takashina, Nobuaki , Kasa, Yasushi , Itano, Kiyoshi , Kawashima, Hiromi , Yamashita, Minoru , Kawamura, Shouichi
IPC: G11C29/00
CPC classification number: G11C29/80 , G11C5/145 , G11C7/067 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/0416 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C16/3472 , G11C16/3481 , G11C29/028 , G11C29/34 , G11C29/46 , G11C29/50 , G11C29/50004 , G11C29/802 , G11C29/82 , G11C29/88 , G11C2029/5004
Abstract: A semiconductor memory device having electrically erasable nonvolatile memory cells to and from which data is automatically written and erased according to an internal algorithm incorporated in said semiconductor memory device. The allowable value of write or erase operations is determined according to the internal algorithm, which is variable. Thus, a device embodying the present invention can carry out a delivery test with "n" rewrite operations at the most, and taking into account deterioration due to an increase in the number of rewrite operations, can guarantee the maximum number of rewrite operations N (N>n) possible by a user.
-
2.发明公开
公开(公告)号：EP1158535A3
公开(公告)日：2002-08-14
申请号：EP01109455.4
申请日：1993-06-25
Applicant: FUJITSU LIMITED
Inventor： Akaogi, Takao , Takashina, Nobuaki , Kasa, Yasushi , Itano, Kiyoshi , Kawashima, Hiromi , Yamashita, Minoru , Kawamura, Shouichi
IPC: G11C16/34
CPC classification number: G11C29/80 , G11C5/145 , G11C7/067 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/0416 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C16/3472 , G11C16/3481 , G11C29/028 , G11C29/34 , G11C29/46 , G11C29/50 , G11C29/50004 , G11C29/802 , G11C29/82 , G11C29/88 , G11C2029/5004
Abstract: A semiconductor memory device having a plurality of word lines (WLs), a plurality of bit lines (BLs), and a memory cell array including a plurality of memory cells (MCs) each formed of a MIS transistor disposed at an intersection of a word line with a bit line. The threshold voltage of each MIS transistor is externally electrically controllable according to charges to be injected to a floating gate thereof, and the floating gates of the MIS transistors are arranged to be simultaneously discharged to collectively erase the memory cells. The invention provides means for saving overerased memory cells of the semiconductor memory device, detecting memory cells that have been overerased by the collective erasing, and writing data to the overerased memory cells, thereby saving them.
-
公开(公告)号：EP0935256B1
公开(公告)日：2002-05-08
申请号：EP99105448.7
申请日：1994-02-08
Applicant: FUJITSU LIMITED
Inventor： Kumakura, Sinsuke , Yamazaki, Hirokazu , Watanabe, Hisayoshi , Kasa, Yasushi
CPC classification number: G11C29/021 , G11C5/14 , G11C5/143 , G11C7/062 , G11C16/04 , G11C29/02 , G11C29/24 , G11C29/44 , G11C29/50 , G11C29/50004 , G11C29/50016 , G11C2029/5006
Abstract: An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3,..., whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.
-
公开(公告)号：EP1158532A2
公开(公告)日：2001-11-28
申请号：EP01109453.9
申请日：1993-06-25
Applicant: FUJITSU LIMITED
Inventor： Akaogi, Takao , Takashina, Nobuaki , Kasa, Yasushi , Itano, Kiyoshi , Kawashima, Hiromi , Yamashita, Minoru , Kawamura, Shouichi
CPC classification number: G11C29/80 , G11C5/145 , G11C7/067 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/0416 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C16/3472 , G11C16/3481 , G11C29/028 , G11C29/34 , G11C29/46 , G11C29/50 , G11C29/50004 , G11C29/802 , G11C29/82 , G11C29/88 , G11C2029/5004
Abstract: A semiconductor memory device having a plurality of word lines (WLs), a plurality of bit lines (BLs), and memory cells (MCs) disposed at intersections of the word lines and bit lines. A decoder circuit (901; 912, 914) selects one memory cell according to an address signal in a normal decoding function, and carries out a full selection operation or a nonselection operation of the word lines or bit lines in a test function. The decoder circuit comprises an output row or a decoding row connected to a first power source (904) and a second power source (905), the first power source supplying a high voltage (Vcc), and the second power source supplying a reference voltage (Vss) or the high voltage in response to a control signal (AH, AL).
Abstract translation: 一种半导体存储器件，具有设置在字线和位线的交叉处的多个字线（WL），多个位线（BL）和存储单元（MC）。 解码器电路（901; 912,914）根据正常解码功能中的地址信号选择一个存储器单元，并且在测试功能中执行字线或位线的完全选择操作或非选择操作。 解码器电路包括连接到第一电源（904）和第二电源（905）的输出行或解码行，第一电源提供高电压（Vcc），第二电源提供参考电压 （Vss）或响应于控制信号（AH，AL）的高电压。
-
公开(公告)号：EP0961289A2
公开(公告)日：1999-12-01
申请号：EP99115179.6
申请日：1992-12-09
Applicant: FUJITSU LIMITED
Inventor： Akaogi, Takao , Kawashima, Hiromi , Takeguchi, Tetsuji , Hagiwara, Ryoji , Kasa, Yasushi , Itano, Kiyoshi , Kawamura, Shouichi , Ogawa, Yasushige
IPC: G11C16/06
CPC classification number: G11C29/82 , G05F3/205 , G11C5/145 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , H03K3/356147 , H03K3/356165 , H03K19/018521 , H03K19/215
Abstract: A flash memory which includes a memory cell array (271) in which a plurality of nonvolatile memory cells that can be erased electrically are set in array and decoding units (273) that decode a plurality of signals and access said memory cell array (271), further comprises: drive units (274) each of which includes a first power terminal (275) and a second power terminal (276), inputs the output of the decoding unit (273), and selectively outputs a voltage applied to the first power terminal (275) or a voltage approximate to that voltage, and a voltage applied to the second power terminal or a voltage approximate to that voltage; the drive unit (274) assuming a first operation mode, in which a first voltage is applied to the first power terminal (275) and a second voltage that is lower than the first voltage is applied to the second power terminal (276), and a second operation mode, in which a third voltage is applied to the first power terminal (275) and a fourth voltage that is higher than the third voltage is applied to the second power terminal (276); and selecting an output voltage depending on whether the first or second operation mode is specified.
Abstract translation: 一种闪速存储器，其包括：存储单元阵列（271），其中可以电擦除的多个非易失性存储单元被设置在阵列中，并且解码多个信号并访问所述存储单元阵列（271）的解码单元（273） 还包括：各包括第一电源端子（275）和第二电源端子（276）的驱动单元（274），输入解码单元（273）的输出，并且选择性地输出施加到第一电源 端子（275）或接近该电压的电压以及施加到第二电源端子的电压或接近该电压的电压; 驱动单元（274）呈现第一操作模式，其中向第一电源端子（275）施加第一电压并且向第二电源端子（276）施加低于第一电压的第二电压，以及以及 第二操作模式，其中向所述第一电源端子（275）施加第三电压，并且向所述第二电源端子（276）施加高于所述第三电压的第四电压; 并根据是否指定第一或第二操作模式来选择输出电压。
-
Patent Agency Ranking6.发明授权
公开(公告)号：EP0262995B1
公开(公告)日：1996-03-27
申请号：EP87401833.6
申请日：1987-08-06
Applicant: FUJITSU LIMITED
Inventor： Kasa, Yasushi
CPC classification number: G11C8/18 , H03K5/1534
-
公开(公告)号：EP0423495A3
公开(公告)日：1992-10-21
申请号：EP90117849.1
申请日：1990-09-17
Applicant: FUJITSU LIMITED
Inventor： Kasa, Yasushi , Arayama, Yuji , Hirayama, Seiji
IPC: G06F11/20
CPC classification number: G11C29/787 , G11C29/838
Abstract: This invention configures a semiconductor memory device in the following manner. The semiconductor contains a first memory part and more than one redundant circuit that is used when the first memory part is faulty, and each redundant circuit memorizes in its status memory part whether a second memory part which becomes a spare cell is in a not-in-use status, in an in-use status or in an out-of-use status, which means that a failure exists in the second memory part. If a second memory part is in the out-of-use status, its access is prohibited, and the other second memory part without a failure is accessed. With this configuration, when a spare cell is confirmed to have a failure after the spare cell is programmed, the spare cell is put in the out-of-use status, thereby preventing the spare cell from being accessed. Consequently, the yield of the semiconductor device is increased.
-
公开(公告)号：EP0419202A3
公开(公告)日：1992-04-01
申请号：EP90310182.2
申请日：1990-09-18
Applicant: FUJITSU LIMITED
Inventor： Kasa, Yasushi
CPC classification number: G11C11/005 , G11C16/102 , G11C17/10
Abstract: A semiconductor memory device with a mask ROM (56) and a PROM (54) whose program characteristics are different is provided with a switching means (58). The switching operation is performed so that the content of the mask ROM (56) becomes effective when the mask ROM is programmed and so that the content of the PROM (54) becomes effective when the PROM is programmed. Thereby, both mask ROM and PROM become programmable, making the semiconductor memory device with mask ROM and PROM effectively operative.
Abstract translation: 具有程序特性不同的掩膜ROM（56）和PROM（54）的半导体存储器装置具有开关装置（58）。 开关操作被执行，使得掩模ROM（56）的内容在掩模ROM被编程时变得有效，并且使得当PROM被编程时PROM（54）的内容变得有效。 由此，掩模ROM和PROM都变得可编程，使得具有掩模ROM和PROM的半导体存储器件有效地工作。
-
公开(公告)号：EP1158532B1
公开(公告)日：2004-06-09
申请号：EP01109453.9
申请日：1993-06-25
Applicant: FUJITSU LIMITED
Inventor： Akaogi, Takao , Takashina, Nobuaki , Kasa, Yasushi , Itano, Kiyoshi , Kawashima, Hiromi , Yamashita, Minoru , Kawamura, Shouichi
IPC: G11C16/08
CPC classification number: G11C29/80 , G11C5/145 , G11C7/067 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/0416 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C16/3472 , G11C16/3481 , G11C29/028 , G11C29/34 , G11C29/46 , G11C29/50 , G11C29/50004 , G11C29/802 , G11C29/82 , G11C29/88 , G11C2029/5004
Abstract: A semiconductor memory device having electrically erasable nonvolatile memory cells to and from which data is automatically written and erased according to an internal algorithm incorporated in said semiconductor memory device. The allowable value of write or erase operations is determined according to the internal algorithm, which is variable. Thus, a device embodying the present invention can carry out a delivery test with "n" rewrite operations at the most, and taking into account deterioration due to an increase in the number of rewrite operations, can guarantee the maximum number of rewrite operations N (N>n) possible by a user.
-
10.发明授权
公开(公告)号：EP1158526B1
公开(公告)日：2003-12-17
申请号：EP01109452.1
申请日：1993-06-25
Applicant: FUJITSU LIMITED
Inventor： Akaogi, Takao , Takashina, Nobuaki , Kasa, Yasushi , Itano, Kiyoshi , Kawashima, Hiromi , Yamashita, Minoru , Kawamura, Shouichi
CPC classification number: G11C29/80 , G11C5/145 , G11C7/067 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/0416 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C16/3472 , G11C16/3481 , G11C29/028 , G11C29/34 , G11C29/46 , G11C29/50 , G11C29/50004 , G11C29/802 , G11C29/82 , G11C29/88 , G11C2029/5004
Abstract: A semiconductor memory device having electrically erasable nonvolatile memory cells to and from which data is automatically written and erased according to an internal algorithm incorporated in said semiconductor memory device. The allowable value of write or erase operations is determined according to the internal algorithm, which is variable. Thus, a device embodying the present invention can carry out a delivery test with "n" rewrite operations at the most, and taking into account deterioration due to an increase in the number of rewrite operations, can guarantee the maximum number of rewrite operations N (N>n) possible by a user.
-
-
-
-
-
-
-
-
-
Search Results
57
records
(took 0.025 seconds)
