A wafer scale integrated circuit wherein at least one of a plurality of functional blocks (2) formed on a semiconductor wafer (1) has its internal defects repaired and has an area which is at least 2.3 cm². The integrated circuit permits the use of a functional block having an area that is much greater than that of the conventional blocks. Therefore, the total length of wirings among the blocks can be shortened to simplify the complex wiring process, the total number of wiring layers can be reduced, and the signal propagation delay time can be shortened, too, making it possible to realize a high packaging density with low redundancy.