公开(公告)号：EP0378115A2

公开(公告)日：1990-07-18

申请号：EP90100171.9

申请日：1990-01-04

申请人： HITACHI, LTD.

发明人： Masuda, Noboru ,  Yasunaga, Moritoshi ,  Yamada, Minoru ,  Masaki, Akira ,  Asai, Mitsuo ,  Hirai, Yuzo ,  Yagyu, Masayoshi ,  Hayashi, Takehisa ,  Doi, Toshio ,  Ishibashi, Kenichi

IPC分类号： G06F15/80

CPC分类号： G06N3/063 ,  G06N3/04

摘要： An information processing system includes a plurality of functional blocks (neurons) (100) and a data bus (300) for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional block (neuron) having the own address designated by the address signal supplied through an address bus (302) outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the addresses signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).

摘要翻译： 信息处理系统包括用于各个功能块（神经元）的输出的多个功能块（神经元）（100）和数据总线（300）。 功能块（神经元）之间的数据交换通过时分基础上的数据总线进行。 为了防止输出冲突或竞争，分别将地址分配给各个块（神经元），使得仅具有通过地址总线（302）提供的地址信号指定的自己的地址的功能块（神经元）输出数据 信号到数据总线上，而其他功能块（神经元）接收数据总线上的信息作为起始于在该时间点指定地址的功能块的信号。 地址顺序更改。 在一轮地址信号期间，数据从给定的功能块（神经元）发送到其他给定的功能块（神经元）。

公开(公告)号：EP0378115A3

公开(公告)日：1993-12-22

申请号：EP90100171.9

申请日：1990-01-04

申请人： HITACHI, LTD.

发明人： Masuda, Noboru ,  Yasunaga, Moritoshi ,  Yamada, Minoru ,  Masaki, Akira ,  Asai, Mitsuo ,  Hirai, Yuzo ,  Yagyu, Masayoshi ,  Hayashi, Takehisa ,  Doi, Toshio ,  Ishibashi, Kenichi

IPC分类号： G06F15/80

CPC分类号： G06N3/063 ,  G06N3/04

摘要： An information processing system includes a plurality of functional blocks (neurons) (100) and a data bus (300) for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional block (neuron) having the own address designated by the address signal supplied through an address bus (302) outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the addresses signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).

公开(公告)号：EP0378115B1

公开(公告)日：1998-09-30

申请号：EP90100171.9

申请日：1990-01-04

申请人： HITACHI, LTD.

发明人： Masuda, Noboru ,  Yasunaga, Moritoshi ,  Yamada, Minoru ,  Masaki, Akira ,  Asai, Mitsuo ,  Hirai, Yuzo ,  Yagyu, Masayoshi ,  Hayashi, Takehisa ,  Doi, Toshio ,  Ishibashi, Kenichi

IPC分类号： G06F15/80

CPC分类号： G06N3/063 ,  G06N3/04

公开(公告)号：EP0308726A3

公开(公告)日：1991-11-21

申请号：EP88114614.6

申请日：1988-09-07

申请人： HITACHI, LTD.

发明人： Masaki, Akira ,  Yasunaga, Moritoshi ,  Mizuishi, Kenichi ,  Mukai, Kiichiro ,  Itoh, Hiroyuki

IPC分类号： H01L27/02

CPC分类号： H01L27/118 ,  G11C29/006 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wafer scale integrated circuit wherein at least one of a plurality of functional blocks (2) formed on a semiconductor wafer (1) has its internal defects repaired and has an area which is at least 2.3 cm². The integrated circuit permits the use of a functional block having an area that is much greater than that of the conventional blocks. Therefore, the total length of wirings among the blocks can be shortened to simplify the complex wiring process, the total number of wiring layers can be reduced, and the signal propagation delay time can be shortened, too, making it possible to realize a high packaging density with low redundancy.

公开(公告)号：EP0308726A2

公开(公告)日：1989-03-29

申请号：EP88114614.6

申请日：1988-09-07

申请人： HITACHI, LTD.

发明人： Masaki, Akira ,  Yasunaga, Moritoshi ,  Mizuishi, Kenichi ,  Mukai, Kiichiro ,  Itoh, Hiroyuki

IPC分类号： H01L27/02

CPC分类号： H01L27/118 ,  G11C29/006 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wafer scale integrated circuit wherein at least one of a plurality of functional blocks (2) formed on a semiconductor wafer (1) has its internal defects repaired and has an area which is at least 2.3 cm². The integrated circuit permits the use of a functional block having an area that is much greater than that of the conventional blocks. Therefore, the total length of wirings among the blocks can be shortened to simplify the complex wiring process, the total number of wiring layers can be reduced, and the signal propagation delay time can be shortened, too, making it possible to realize a high packaging density with low redundancy.

摘要翻译： 一种晶片级集成电​​路，其中形成在半导体晶片（1）上的多个功能块（2）中的至少一个具有修复的内部缺陷并且具有至少2.3cm 2的面积。 集成电路允许使用具有比常规块的面积大得多的面积的功能块。 因此，可以缩短块之间的布线总长度，简化复杂的布线处理，可以减少布线层的总数，并且可以缩短信号传播延迟时间，能够实现高封装 密度低，冗余度低。