发明公开
- 专利标题： Delay circuit
- 专利标题（中）： 延迟电路
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申请号： EP89301628.7申请日： 1989-02-20
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公开(公告)号： EP0330405A2公开(公告)日： 1989-08-30
- 发明人: Seki, Teruo , Iwase, Akihiro , Nagai, Sinzi
- 申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
- 申请人地址： 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 JP
- 专利权人： FUJITSU LIMITED,FUJITSU VLSI LIMITED
- 当前专利权人： FUJITSU LIMITED,FUJITSU VLSI LIMITED
- 当前专利权人地址： 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 JP
- 代理机构： Billington, Lawrence Emlyn
- 优先权： JP38809/88 19880222
- 主分类号： H03K5/13
- IPC分类号： H03K5/13
摘要：
A delay circuit having two or more first switching transistors (51,52) connected in series between an output terminal (OUT) and a power source line (Vcc), and two or more second switching transistors (53,54) connected in series between the output terminal (OUT) and another power source line (Vss), the first and the second switching transistors operating in a complementary manner in response to an input signal (IN), one or more pairs of nodes (N₅,N₇) of the switching transistors being connected by one or more current paths (55) each connected to at least one capacitor (C₃,C₆) whereby an input signal is transmitted to the output terminal (OUT) at a specified interval defined by the capacitance of the or each capacitor.
公开/授权文献
- EP0330405B1 Delay circuit 公开/授权日：1992-07-08
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