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    Delay circuit
    1.
    发明公开
    Delay circuit 失效
    延迟电路

    公开(公告)号：EP0330405A2

    公开(公告)日：1989-08-30

    申请号：EP89301628.7

    申请日：1989-02-20

    申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

    发明人： Seki, Teruo ,  Iwase, Akihiro ,  Nagai, Sinzi

    IPC分类号： H03K5/13

    CPC分类号： H03K5/133 ,  H03K2005/00215

    摘要： A delay circuit having two or more first switching transistors (51,52) connected in series between an output terminal (OUT) and a power source line (Vcc), and two or more second switching transistors (53,54) connected in series between the output terminal (OUT) and another power source line (Vss), the first and the second switching transistors operating in a complementary manner in response to an input signal (IN), one or more pairs of nodes (N₅,N₇) of the switching transistors being connected by one or more current paths (55) each connected to at least one capacitor (C₃,C₆) whereby an input signal is transmitted to the output terminal (OUT) at a specified interval defined by the capacitance of the or each capacitor.

    摘要翻译： 一种延迟电路，具有串联连接在输出端（OUT）和电源线（Vcc）之间的两个或更多个第一开关晶体管（51,52），以及两个或更多个第二开关晶体管（53,54） 所述输出端（OUT）和另一电源线（Vss），所述第一和第二开关晶体管响应于输入信号（IN）以互补方式工作，所述第一和第二开关晶体管的一对或多对节点（N 5，N 7） 开关晶体管通过一个或多个电流路径（55）连接，每个电流路径连接到至少一个电容器（C 3，C 6），由此输入信号以由该电容器或每个电容器的电容限定的特定间隔传输到输出端子（OUT） 电容。

    Delay circuit
    3.
    发明公开
    Delay circuit 失效
    延时电路

    公开(公告)号：EP0330405A3

    公开(公告)日：1989-11-02

    申请号：EP89301628.7

    申请日：1989-02-20

    申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

    发明人： Seki, Teruo ,  Iwase, Akihiro ,  Nagai, Sinzi

    IPC分类号： H03K5/13

    CPC分类号： H03K5/133 ,  H03K2005/00215

    摘要： A delay circuit having two or more first switching transistors (51,52) connected in series between an output terminal (OUT) and a power source line (Vcc), and two or more second switching transistors (53,54) connected in series between the output terminal (OUT) and another power source line (Vss), the first and the second switching transistors operating in a complementary manner in response to an input signal (IN), one or more pairs of nodes (N₅,N₇) of the switching transistors being connected by one or more current paths (55) each connected to at least one capacitor (C₃,C₆) whereby an input signal is transmitted to the output terminal (OUT) at a specified interval defined by the capacitance of the or each capacitor.