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公开(公告)号：EP0330405B1
公开(公告)日：1992-07-08
申请号：EP89301628.7
申请日：1989-02-20
发明人： Seki, Teruo , Iwase, Akihiro , Nagai, Sinzi
IPC分类号： H03K5/13
CPC分类号： H03K5/133 , H03K2005/00215
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公开(公告)号：EP0330405A3
公开(公告)日：1989-11-02
申请号：EP89301628.7
申请日：1989-02-20
发明人： Seki, Teruo , Iwase, Akihiro , Nagai, Sinzi
IPC分类号： H03K5/13
CPC分类号： H03K5/133 , H03K2005/00215
摘要： A delay circuit having two or more first switching transistors (51,52) connected in series between an output terminal (OUT) and a power source line (Vcc), and two or more second switching transistors (53,54) connected in series between the output terminal (OUT) and another power source line (Vss), the first and the second switching transistors operating in a complementary manner in response to an input signal (IN), one or more pairs of nodes (N₅,N₇) of the switching transistors being connected by one or more current paths (55) each connected to at least one capacitor (C₃,C₆) whereby an input signal is transmitted to the output terminal (OUT) at a specified interval defined by the capacitance of the or each capacitor.
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公开(公告)号：EP0439158A2
公开(公告)日：1991-07-31
申请号：EP91100855.5
申请日：1991-01-24
发明人： Seki, Teruo
IPC分类号： H03K19/0175 , H03K17/687
CPC分类号： H03K17/6872 , H03K19/017518
摘要： A input signal is received by a level shift circuit (41) to generate a plurality of level-shifted output signals (A, B,..., A , B ,...) which have different shift amounts to each other. A switch circuit (42), selectively outputs the level-shifted output signals in response to a logic level of the input signal. The switch circuit selects a signal having a higher potential from the level-shifted output signals when the logic level of the input signal indicates a first level, and selects a signal having a lower potential from said level-shifted output signals when the logic level of the input signal indicates a second level.
摘要翻译： 输入信号由电平移位电路（41）接收以产生彼此具有不同移位量的多个电平移位输出信号（A，B，...，A，B，...）。 开关电路（42）响应于输入信号的逻辑电平有选择地输出电平移位的输出信号。 当输入信号的逻辑电平指示第一电平时，开关电路从电平移位输出信号中选择具有较高电位的信号，并且当逻辑电平为0时，从所述电平移位输出信号中选择具有较低电位的信号 输入信号指示第二级。
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公开(公告)号：EP0439158A3
公开(公告)日：1991-11-27
申请号：EP91100855.5
申请日：1991-01-24
发明人： Seki, Teruo
IPC分类号： H03K19/0175 , H03K17/687
CPC分类号： H03K17/6872 , H03K19/017518
摘要： A input signal is received by a level shift circuit (41) to generate a plurality of level-shifted output signals (A, B,..., A , B ,...) which have different shift amounts to each other. A switch circuit (42), selectively outputs the level-shifted output signals in response to a logic level of the input signal. The switch circuit selects a signal having a higher potential from the level-shifted output signals when the logic level of the input signal indicates a first level, and selects a signal having a lower potential from said level-shifted output signals when the logic level of the input signal indicates a second level.
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公开(公告)号：EP0439158B1
公开(公告)日：1996-05-08
申请号：EP91100855.5
申请日：1991-01-24
发明人： Seki, Teruo
IPC分类号： H03K19/0175 , H03K17/687
CPC分类号： H03K17/6872 , H03K19/017518
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公开(公告)号：EP0330405A2
公开(公告)日：1989-08-30
申请号：EP89301628.7
申请日：1989-02-20
发明人： Seki, Teruo , Iwase, Akihiro , Nagai, Sinzi
IPC分类号： H03K5/13
CPC分类号： H03K5/133 , H03K2005/00215
摘要： A delay circuit having two or more first switching transistors (51,52) connected in series between an output terminal (OUT) and a power source line (Vcc), and two or more second switching transistors (53,54) connected in series between the output terminal (OUT) and another power source line (Vss), the first and the second switching transistors operating in a complementary manner in response to an input signal (IN), one or more pairs of nodes (N₅,N₇) of the switching transistors being connected by one or more current paths (55) each connected to at least one capacitor (C₃,C₆) whereby an input signal is transmitted to the output terminal (OUT) at a specified interval defined by the capacitance of the or each capacitor.
摘要翻译： 一种延迟电路，具有串联连接在输出端（OUT）和电源线（Vcc）之间的两个或更多个第一开关晶体管（51,52），以及两个或更多个第二开关晶体管（53,54） 所述输出端（OUT）和另一电源线（Vss），所述第一和第二开关晶体管响应于输入信号（IN）以互补方式工作，所述第一和第二开关晶体管的一对或多对节点（N 5，N 7） 开关晶体管通过一个或多个电流路径（55）连接，每个电流路径连接到至少一个电容器（C 3，C 6），由此输入信号以由该电容器或每个电容器的电容限定的特定间隔传输到输出端子（OUT） 电容。
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公开(公告)号：EP0107395A3
公开(公告)日：1986-07-02
申请号：EP83305879
申请日：1983-09-29
申请人： FUJITSU LIMITED
发明人： Seki, Teruo , Yamauchi, Takahiko , Aoyama, Keizo
IPC分类号： G11C08/00 , H03K19/096
CPC分类号： G11C8/10
摘要： A decoder circuit receiving decoder inputs (A o to A m ) and producing decoder outputs (X 4 ). The decoder inputs are applied, as control inputs, to respective input transistors (P 70 to P 7m ) connected in parallel with each other. The outputs thereof are commonly connected to a node (Q). The node is provided with a gate transistor (N 70 ) and latch transistors (LT). The gate transistor is operative to invert the level at the node momentarily every time the decoder circuit is switched from a nonselection state to a selection state. The latch transistors maintain the level at the node as the decoder output level.
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公开(公告)号：EP0100166A3
公开(公告)日：1986-02-12
申请号：EP83303915
申请日：1983-07-05
申请人： FUJITSU LIMITED
发明人： Yamauchi, Takahiko , Seki, Teruo , Aoyama, Keizo
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L21/76895 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： in a semiconductor device including a connection structure comprising a first conductive layer 14 formed in or on a semiconductor substrate 11, a second conductive layer 15 arranged adjacent the first conductive layer 14, and a third conductive layer 17 connecting the first conductive layer 14, and to the second conductive layer 15. The third conductive layer 17 is in contact with the first 14 and second 15 conductive layers in a contact region 16'. One dimension of the portion of the second conductive layer 15 in the contact region 16' varies which enables the size of the contact region 16' to be reduced whilst still ensuring a positive connection between the first 14 and second 15, conductive layers even in the event of their misregistry.
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公开(公告)号：EP0087979A3
公开(公告)日：1986-01-08
申请号：EP83301104
申请日：1983-03-02
申请人： FUJITSU LIMITED
发明人： Aoyama, Keizo , Yamauchi, Takahiko , Seki, Teruo
CPC分类号： G11C5/063 , G11C5/005 , G11C5/14 , G11C11/4125 , H01L23/556 , H01L27/1112 , H01L2924/0002 , Y10S257/927 , H01L2924/00
摘要： A static-type semiconductor memory device having a three-layer structure; the gate-electrode wiring lines being formed by a first conductive layer of, for example, polycrystalline silicon; the word lines, the ground lines, and the power supply lines being formed by a second conductive layer of, for example, aluminum; and the bit lines being formed by a third conductive layer of, for example, aluminum; the bit lines extending in a column direction, and the ground lines extending in a row direction; whereby an improved integration degree, an improved operating speed, an improved manufacturing yield, and a countermeasure for soft errors due to alpha particles are attained.
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公开(公告)号：EP0090591A2
公开(公告)日：1983-10-05
申请号：EP83301617.3
申请日：1983-03-23
申请人： FUJITSU LIMITED
发明人： Aoyama, Keizo , Yamauchi, Takahiko , Seki, Teruo
CPC分类号： G11C7/1006 , G11C11/419
摘要： A semiconductor memory device comprising bit lines, word lines, memory cells arranged at the intersections of the bit lines and the word lines, data buses, and transfer gate transistors connected between the bit lines and the data buses, an information signal being read out to the data buses from the memory cells through the bit lines by turning on the transfer gate transistors and the transfer gate transistors having a threshold voltage smaller than that of the transistors used in the other circuits of the semiconductor memory device.
摘要翻译： 一种半导体存储器件，包括位线，字线，布置在位线和字线的交叉点处的存储单元，数据总线和连接在位线和数据总线之间的传输门晶体管，信息信号被读出 通过导通传输门晶体管和传输门晶体管从存储单元通过位线的数据总线，传输门晶体管的阈值电压小于半导体存储器件的其他电路中使用的晶体管的阈值电压。
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