A sample-hold circuit comprises a large number of sample-hold elements (2Am, ..., 2Am+5), and a mult-­stage shift register (7A) for controlling sampling timings of the sample-hold elements, including a large number of stages corresponding to respective sample-hold elements, characterized in that each of stages (20, 20m, ..., 20m+5) of the multi-stage shift register includes an input gate (21, 21m, ..., 21m+5) for taking a signal shifted from the preceding stage thereinto, an output gate (22, 22m, ..., 22m+5) for shifting the signal taken in by the input gate to the succeeding stage, respective sampling timings of said sample-hold elements corresponding to respective stages being determined by signals taken in between the input and output gates through the input gates at the respective stages. Waveforms of output signals from respective stages for determining the sampling timing are not affected by interstage wiring capacity. Accordingly, where a multi-­stage shift register is made up as a folded array, unevenness occurs in the interstage wiring capacity, but such an unevenness has no bad influence on the sampling timing.