A low current CMOS translator arrangement is disclosed that utilizes a low current inverting stage (102), having a peak current requirement, fed by a constant current source (104) at a supply node (+V) that also has a capacitor (106) coupled to it. This low current inverter (102) is useful for a number of applications, including generating a sinusoidal signal when it is coupled to a crystal. When one or more are cascaded and coupled to a square wave input signal, the arrangement becomes a low current translator that level-shifts, or translates, the input signal having a first voltage range to a translated square wave output signal having a second voltage range.
In another embodiment called a low current squaring translator, a squaring stage is coupled between the low current inverter and a low current translator that includes one or more inverting stage.s This arrangement is able to achieve an output signal that maintains a precise duty cycle with low noise at a very low current.