发明公开
EP0357213A2 Low power sense amplifier for programmable logic device
失效
Leissungfüreine programmierbare logische Einrichtung的Leseverstärkermit niedriger。
- 专利标题： Low power sense amplifier for programmable logic device
- 专利标题（中）： Leissungfüreine programmierbare logische Einrichtung的Leseverstärkermit niedriger。
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申请号： EP89307499.7申请日： 1989-07-24
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公开(公告)号： EP0357213A2公开(公告)日： 1990-03-07
- 发明人: Pathak, Jagdish , Kurkowski, Hal , Douglas, Stephen M. , Vider, Dov-Ami
- 申请人： CYPRESS SEMICONDUCTOR CORPORATION
- 申请人地址： 3901 North First Street San Jose California 95134 US
- 专利权人： CYPRESS SEMICONDUCTOR CORPORATION
- 当前专利权人： CYPRESS SEMICONDUCTOR CORPORATION
- 当前专利权人地址： 3901 North First Street San Jose California 95134 US
- 代理机构： Wombwell, Francis
- 优先权： US240089 19880902
- 主分类号： G11C7/06
- IPC分类号： G11C7/06 ; G05F3/24 ; G11C16/06
摘要：
The invention pertains to a circuit for controlling the power to a plurality of sense amplifiers used for sensing data on data lines in an array of floating gate storage cells, wherein the data stored in the array is sensed at regular intervals. The circuit includes a first plurality of data paths through the array, and a second data path containing replications of all necessary circuit elements in the first plurality of data paths to assure that the data delay through the second path equals or exceeds the maximum delay in any of the first plurality of data paths. A clock (CLK) is used to provide an initiation signal which starts the propogation of input data through the array. The control circuit of the invention reduces the power consumption of the sense amplifiers because they are powered only during the duration of data transmission, but are otherwise powered down.
公开/授权文献
- EP0357213B1 Low power sense amplifier for programmable logic device 公开/授权日：1994-09-07
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