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公开(公告)号：EP0357213B1
公开(公告)日：1994-09-07
申请号：EP89307499.7
申请日：1989-07-24
CPC分类号： H03K19/17712 , G05F3/245 , G11C16/26 , H03K5/04 , H03K19/0016
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2.发明公开Low power sense amplifier for programmable logic device 失效Leissungfüreine programmierbare logische Einrichtung的Leseverstärkermit niedriger。
公开(公告)号：EP0357213A2
公开(公告)日：1990-03-07
申请号：EP89307499.7
申请日：1989-07-24
CPC分类号： H03K19/17712 , G05F3/245 , G11C16/26 , H03K5/04 , H03K19/0016
摘要： The invention pertains to a circuit for controlling the power to a plurality of sense amplifiers used for sensing data on data lines in an array of floating gate storage cells, wherein the data stored in the array is sensed at regular intervals. The circuit includes a first plurality of data paths through the array, and a second data path containing replications of all necessary circuit elements in the first plurality of data paths to assure that the data delay through the second path equals or exceeds the maximum delay in any of the first plurality of data paths. A clock (CLK) is used to provide an initiation signal which starts the propogation of input data through the array. The control circuit of the invention reduces the power consumption of the sense amplifiers because they are powered only during the duration of data transmission, but are otherwise powered down.
摘要翻译： 本发明涉及一种用于控制用于感测浮动栅极存储单元阵列中的数据线上的数据的多个读出放大器的功率的电路，其中以规则的间隔感测存储在阵列中的数据。 电路包括穿过该阵列的第一多个数据路径，以及第二数据路径，其包含第一多个数据路径中的所有必需的电路元件的复制，以确保通过第二路径的数据延迟等于或超过任何 的第一多个数据路径。 时钟（CLK）用于提供启动信号，启动信号通过阵列传播输入数据。 本发明的控制电路降低了读出放大器的功耗，因为它们仅在数据传输期间被供电，而是被断电。
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公开(公告)号：EP0357213A3
公开(公告)日：1991-05-22
申请号：EP89307499.7
申请日：1989-07-24
CPC分类号： H03K19/17712 , G05F3/245 , G11C16/26 , H03K5/04 , H03K19/0016
摘要： The invention pertains to a circuit for controlling the power to a plurality of sense amplifiers used for sensing data on data lines in an array of floating gate storage cells, wherein the data stored in the array is sensed at regular intervals. The circuit includes a first plurality of data paths through the array, and a second data path containing replications of all necessary circuit elements in the first plurality of data paths to assure that the data delay through the second path equals or exceeds the maximum delay in any of the first plurality of data paths. A clock (CLK) is used to provide an initiation signal which starts the propogation of input data through the array. The control circuit of the invention reduces the power consumption of the sense amplifiers because they are powered only during the duration of data transmission, but are otherwise powered down.
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