发明公开
EP0394499A1 APPARATUS FOR MULTIPLICATION, DIVISION AND EXTRACTION OF SQUARE ROOT
失效
VORRICHTUNG ZUMVERVIELFÄLTIGEN,TEILEN UND ZIEHEN DER QUADRATWURZEL。
- 专利标题: APPARATUS FOR MULTIPLICATION, DIVISION AND EXTRACTION OF SQUARE ROOT
- 专利标题(中): VORRICHTUNG ZUMVERVIELFÄLTIGEN,TEILEN UND ZIEHEN DER QUADRATWURZEL。
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申请号: EP89912134.7申请日: 1989-11-02
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公开(公告)号: EP0394499A1公开(公告)日: 1990-10-31
- 发明人: NARITA, Masahisa , KAZIWARA, Hisashi , ASAI, Takeshi , MORINAGA, Shigeki , KIDA, Hiroyuki , WATABE, Mitsuru , NAKAMIKAWA, Tetsuaki , KAWASAKI, Shunpei , TATEZAKI, Junichi , NAKAGAWA, Norio , KASHIWAGI, Yugo
- 申请人: Hitachi, Ltd. , Hitachi Engineering Co., Ltd.
- 申请人地址: 6, Kanda Surugadai 4-chome Chiyoda-ku, Tokyo JP
- 专利权人: Hitachi, Ltd.,Hitachi Engineering Co., Ltd.
- 当前专利权人: Hitachi, Ltd.,Hitachi Engineering Co., Ltd.
- 当前专利权人地址: 6, Kanda Surugadai 4-chome Chiyoda-ku, Tokyo JP
- 代理机构: Beetz & Partner
- 优先权: JP27724288 19881104; JP29024888 19881118; JP30996888 19881209
- 国际公布: WO1990005335 19900517
- 主分类号: G06F7/52
- IPC分类号: G06F7/52 ; G06F7/552
摘要:
An apparatus for multiplication, division and extraction of the square root which determines the value of a function of multiplication, division or extraction of the square root by iterated approximation includes a multiplier, adder/subtracter and shifter each having a predetermined bit width and connected to a bus. The output of the multiplier is inputted to the adder/subtractor or to the shifter and the result is again inputted to the multiplier through the bus. This operation is repeated. A shifter and a calculator connected to a second bus through a switch have a bit width greater than the predetermined bit width, are used for large-scale calculation and prevent a drop in calculation speed.
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