公开(公告)号：EP0394499B1

公开(公告)日：1997-10-08

申请号：EP89912134.7

申请日：1989-11-02

申请人： HITACHI, LTD. ,  Hitachi Engineering Co., Ltd.

发明人： NARITA, Masahisa ,  KAZIWARA, Hisashi ,  ASAI, Takeshi ,  MORINAGA, Shigeki ,  KIDA, Hiroyuki ,  WATABE, Mitsuru ,  NAKAMIKAWA, Tetsuaki ,  KAWASAKI, Shunpei ,  TATEZAKI, Junichi ,  NAKAGAWA, Norio ,  KASHIWAGI, Yugo

IPC分类号： G06F7/52 ,  G06F7/552

CPC分类号： G06F7/57 ,  G06F7/4873 ,  G06F7/49957 ,  G06F7/535 ,  G06F7/5525 ,  G06F2207/3816 ,  G06F2207/5355 ,  G06F2207/5356

摘要： An apparatus for multiplication, division and extraction of the square root which determines the value of a function of multiplication, division or extraction of the square root by iterated approximation includes a multiplier, adder/subtractor and shifter each having a predetermined bit width and connected to a bus. The output of the multiplier is inputted to the adder/subtractor or to the shifter and the result is again inputted to the multiplier through the bus. This operation is repeated. A shifter and a calculator connected to a second bus through a switch have a bit width greater than the predetermined bit width, are used for large-scale calculation and prevent a drop in calculation speed.

公开(公告)号：EP0394499A1

公开(公告)日：1990-10-31

申请号：EP89912134.7

申请日：1989-11-02

申请人： Hitachi, Ltd. ,  Hitachi Engineering Co., Ltd.

发明人： NARITA, Masahisa ,  KAZIWARA, Hisashi ,  ASAI, Takeshi ,  MORINAGA, Shigeki ,  KIDA, Hiroyuki ,  WATABE, Mitsuru ,  NAKAMIKAWA, Tetsuaki ,  KAWASAKI, Shunpei ,  TATEZAKI, Junichi ,  NAKAGAWA, Norio ,  KASHIWAGI, Yugo

IPC分类号： G06F7/52 ,  G06F7/552

CPC分类号： G06F7/57 ,  G06F7/4873 ,  G06F7/49957 ,  G06F7/535 ,  G06F7/5525 ,  G06F2207/3816 ,  G06F2207/5355 ,  G06F2207/5356

摘要： An apparatus for multiplication, division and extraction of the square root which determines the value of a function of multiplication, division or extraction of the square root by iterated approximation includes a multiplier, adder/subtracter and shifter each having a predetermined bit width and connected to a bus. The output of the multiplier is inputted to the adder/subtractor or to the shifter and the result is again inputted to the multiplier through the bus. This operation is repeated. A shifter and a calculator connected to a second bus through a switch have a bit width greater than the predetermined bit width, are used for large-scale calculation and prevent a drop in calculation speed.

摘要翻译： 用于乘法，除法和提取平方根，用于通过迭代近似确定平方根的乘法，除法或提取函数的值。 乘法器，加法器/减法器和移位器各自具有预定的位宽并连接到总线。 乘法器的输出被输入到加法器/减法器或移位器，并且结果再次通过总线输入到乘法器。 重复该操作。 通过开关连接到第二总线的移位器和计算器具有大于预定位宽的位宽度，用于大规模计算，并防止计算速度下降。

公开(公告)号：EP0185098A1

公开(公告)日：1986-06-25

申请号：EP85902655.1

申请日：1985-05-29

申请人： HITACHI, LTD.

发明人： FUNABASHI, Tsuneo ,  IWASAKI, Kazuhiko ,  YAMAGUCHI, Noboru ,  SHIMURA, Takanori ,  TATEZAKI, Junichi

IPC分类号： G06F13/12

CPC分类号： G06F13/385 ,  G06F13/124

摘要： A control integrated circuit of the invention is based upon a hierarchical processor structure. A microprogram controller (211) is employed for a high-order processor to give sophisticated functions. A plurality of finite-state transition machines (208, 209) are employed for a low-order processor to increase the speed of operation. The control function for an external input/output device is divided and is executed by a plurality of finite-state transition machines (208,209), the performance thereof being controlled by the microprogram controller (211). According to the present invention, a new control function is processed by adding a finite-state transition machine (210). Namely, the invention provides the general structure of an integrated circuit for controlling various input/output devices.

摘要翻译： 本发明的控制集成电路基于分级处理器结构。 微程序控制器（211）用于高阶处理器以提供复杂的功能。 多个有限状态转换机（208,209）被用于低阶处理器以提高操作速度。 用于外部输入/输出设备的控制功能被分割并由多个有限状态转换机执行，其性能由微程序控制器（211）控制。 根据本发明，通过添加有限状态转换机（210）来处理新的控制功能。 即，本发明提供了用于控制各种输入/输出装置的集成电路的一般结构。