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1.发明公开APPARATUS FOR MULTIPLICATION, DIVISION AND EXTRACTION OF SQUARE ROOT 失效VORRICHTUNG ZUMVERVIELFÄLTIGEN，TEILEN UND ZIEHEN DER QUADRATWURZEL。
公开(公告)号：EP0394499A1
公开(公告)日：1990-10-31
申请号：EP89912134.7
申请日：1989-11-02
发明人： NARITA, Masahisa , KAZIWARA, Hisashi , ASAI, Takeshi , MORINAGA, Shigeki , KIDA, Hiroyuki , WATABE, Mitsuru , NAKAMIKAWA, Tetsuaki , KAWASAKI, Shunpei , TATEZAKI, Junichi , NAKAGAWA, Norio , KASHIWAGI, Yugo
CPC分类号： G06F7/57 , G06F7/4873 , G06F7/49957 , G06F7/535 , G06F7/5525 , G06F2207/3816 , G06F2207/5355 , G06F2207/5356
摘要： An apparatus for multiplication, division and extraction of the square root which determines the value of a function of multiplication, division or extraction of the square root by iterated approximation includes a multiplier, adder/subtracter and shifter each having a predetermined bit width and connected to a bus. The output of the multiplier is inputted to the adder/subtractor or to the shifter and the result is again inputted to the multiplier through the bus. This operation is repeated. A shifter and a calculator connected to a second bus through a switch have a bit width greater than the predetermined bit width, are used for large-scale calculation and prevent a drop in calculation speed.
摘要翻译： 用于乘法，除法和提取平方根，用于通过迭代近似确定平方根的乘法，除法或提取函数的值。 乘法器，加法器/减法器和移位器各自具有预定的位宽并连接到总线。 乘法器的输出被输入到加法器/减法器或移位器，并且结果再次通过总线输入到乘法器。 重复该操作。 通过开关连接到第二总线的移位器和计算器具有大于预定位宽的位宽度，用于大规模计算，并防止计算速度下降。
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2.发明授权
公开(公告)号：EP0394499B1
公开(公告)日：1997-10-08
申请号：EP89912134.7
申请日：1989-11-02
发明人： NARITA, Masahisa , KAZIWARA, Hisashi , ASAI, Takeshi , MORINAGA, Shigeki , KIDA, Hiroyuki , WATABE, Mitsuru , NAKAMIKAWA, Tetsuaki , KAWASAKI, Shunpei , TATEZAKI, Junichi , NAKAGAWA, Norio , KASHIWAGI, Yugo
CPC分类号： G06F7/57 , G06F7/4873 , G06F7/49957 , G06F7/535 , G06F7/5525 , G06F2207/3816 , G06F2207/5355 , G06F2207/5356
摘要： An apparatus for multiplication, division and extraction of the square root which determines the value of a function of multiplication, division or extraction of the square root by iterated approximation includes a multiplier, adder/subtractor and shifter each having a predetermined bit width and connected to a bus. The output of the multiplier is inputted to the adder/subtractor or to the shifter and the result is again inputted to the multiplier through the bus. This operation is repeated. A shifter and a calculator connected to a second bus through a switch have a bit width greater than the predetermined bit width, are used for large-scale calculation and prevent a drop in calculation speed.
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