A digital loop filter translates a multi-bit phase error input into a high resolution control signal utilizable as an advance-retard control for a multi-phase clock generator. The digital filter couples the multi-bit phase error input to the clock generator via a pulse density modulation (PDM) accumulator, providing multi-phase adjustment in a single sample clock cycle based on the overflow or underflow of the PDM accumulator. Variable PDM cycles are used to control loop filter bandwidth, permitting adjustable capture sequences. Thus, real proportional control of the multi-phase clock generator is limited only by the word size of the phase error input.